Hermetic wafer level packaging

• US 8,648,468 B2
• Filed: 07/29/2010
• Issued: 02/11/2014
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Richard, Liu, Martin, Chu, Chia-Hua, Hsieh, Yuan-Chih, Lin, Chung-Hsien, Chao, Lan-Lin, Cheng, Chun-Wen, Liu, Mingo
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US12/846,504
• Publication Number:
  US 20120025389A1
• Time in Patent Office: 1,293 Days
• Field of Search: 257/773, 257/E23.141, 257685-686, 257/774, 257/777
• US Class Current: 257/773
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Claims

1. An apparatus, comprising:

a first substrate having a plurality of microelectronic components and a multilayer interconnect (MLI) structure containing a plurality of metal lines and vias that provide interconnections for the microelectronic components, wherein the first substrate further includes a first bonding pad that is one of the metal lines at a topmost layer of the MLI structure, the first bonding pad including a first material; and

a second substrate having a second bonding pad, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy;

wherein;

a portion of the second substrate is bonded to the first substrate through the first and second bonding pads;

the first substrate includes an integrated circuit device; and

the second substrate includes one of;

a through-silicon via (TSV) and a micro-electrical-mechanical system (MEMS) device.

2. The apparatus of claim 1, wherein the second bonding pad is electrically coupled to the TSV.

3. The apparatus of claim 1, wherein the titanium alloy has a chemical composition of TixAlyCuz, wherein x, y, and z are each in a range from 0 to 100.

4. The apparatus of claim 1, wherein the first substrate has a third bonding pad that includes a third material;

and further including a third substrate having a fourth bonding pad that includes a fourth material different from the third material, one of the third and fourth materials being aluminum, and the other thereof being a titanium alloy;

wherein;

the first and third substrates are bonded together through the third and fourth bonding pads; and

the portion of the second substrate is surrounded by the first and third substrates.

5. The apparatus of claim 1, wherein:

the first substrate contains a recess that exposes a portion of the first bonding pad; and

the second bonding pad is disposed within the recess.

6. A wafer level packaging, comprising:

a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material; and

a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based;

wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers; and

wherein the first wafer include a concave recess that exposes the first bonding layer, and wherein the second bonding layer is disposed within the concave recess.

7. The packaging of claim 6, wherein the first wafer has a third bonding layer that includes a third material;

and further including a capping layer having a fourth bonding layer that includes a fourth material different from the third material, one of the third and fourth materials being aluminum-based, and the other thereof being titanium-based; and

wherein the first wafer and the capping layer are bonded together through the third and fourth bonding layers.

8. The packaging of claim 6, wherein the second wafer includes a micro-electrical-mechanical system (MEMS) device that is hermetically sealed by the capping layer and the first wafer.

9. The packaging of claim 6, wherein the titanium-based material is an alloy made of materials selected from the group consisting of:

titanium, aluminum, copper, and germanium.

10. The packaging of claim 6, wherein:

the second wafer has a through-silicon via that extends through the second wafer; and

the second bonding layer is coupled to the through-silicon via.

11. The packaging of claim 6, wherein the first wafer has an interconnect structure that includes a top metal layer, the first bonding layer being a portion of the top metal layer.

12. A packaged device, comprising:

a first bonding pad on a first wafer, the first bonding pad including a first bonding material, the first wafer including a micro-electrical-mechanical system (MEMS) device;

a second bonding pad on a protruding portion of a second wafer that protrudes towards the first wafer, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy; and

a bond between the first and second wafers, at the first and second bonding pads;

wherein the MEMS device of the first wafer is circumferentially surrounded by the protruding portion of the second wafer.

13. The device of claim 12, wherein the bond is of a metal diffusion, wherein metal ions from the first bonding pad have been diffused into the second bonding pad.

14. The device of claim 13, wherein the bond is of a metal diffusion, wherein metal ions from the second bonding pad have been diffused into the first bonding pad.

15. The device of claim 12, wherein the bond provides a hermetic seal of the MEMS device.

16. The device of claim 12, wherein the first bond pad includes aluminum.

17. The device of claim 16, wherein the second bond pad includes titanium.

18. The device of claim 12, wherein the first wafer includes a multilayer interconnect (MLI) structure containing a plurality of metal lines and vias, and wherein the first bond pad is a one of the metal lines as a topmost metal layer of the MLI structure.