Method for driving semiconductor device

• US 8,649,208 B2
• Filed: 05/17/2012
• Issued: 02/11/2014
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori, Inoue, Hiroki, Nagatsuka, Shuhei
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/473,752
• Publication Number:
  US 20120294070A1
• Time in Patent Office: 635 Days
• Field of Search: 365/149, 365/203, 365/207
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.

Claims

1. A method for driving a semiconductor device,

the semiconductor device comprising a memory cell:

wherein in the memory cell, a source electrode of a first transistor is electrically connected to a bit line, a drain electrode of the first transistor is electrically connected to a source line, and a gate electrode of the first transistor, a drain electrode of a second transistor, and one electrode of a capacitor are electrically connected to each other to form a node where a potential is held,

the method comprising the steps of, in a data reading period;

supplying a ground potential to the source line;

connecting the bit line to a precharge potential supplying line so that the bit line is set to a precharge potential;

disconnecting the bit line from the precharge potential supplying line so that a potential of the bit line changes depending on a potential held in the node; and

reading a change in potential of the bit line to read the potential held in the node.

2. The method for driving a semiconductor device, according to claim 1, wherein the first transistor is a p-channel transistor.

3. The method for driving a semiconductor device, according to claim 1, wherein the first transistor is an n-channel transistor.

4. The method for driving a semiconductor device, according to claim 1, wherein a channel formation region of the second transistor includes an oxide semiconductor.

5. A method for driving a semiconductor device,

the semiconductor device comprising a memory cell array comprising a plurality of signal lines, a plurality of bit lines, a plurality of source lines, a plurality of capacitor lines, and a plurality of memory cells,

wherein in one of the plurality of memory cells, a source electrode of a first transistor is electrically connected to one of the plurality of bit lines, a drain electrode of the first transistor is electrically connected to one of the plurality of source lines, a gate electrode of the first transistor, a drain electrode of a second transistor, and one electrode of a capacitor are electrically connected to each other, the other electrode of the capacitor is electrically connected to one of the plurality of capacitor lines, a source electrode of the second transistor is electrically connected to one of the plurality of signal lines, and a node where a potential supplied from the one of the plurality of signal lines is held is formed between the gate electrode of the first transistor, the drain electrode of the second transistor, and the one electrode of the capacitor,

the method comprising the steps of, in a data reading period:

supplying a ground potential to one of the plurality of capacitor lines which is electrically connected to one of the plurality of memory cells, so that the one of the plurality of memory cells is to be selected;

supplying a ground potential to one of the plurality of source lines which is electrically connected to the selected memory cell;

electrically connecting one of the plurality of bit lines to a precharge potential supplying line so that the one of the plurality of bit lines is set to a precharge potential;

disconnecting the one of the plurality of bit lines of the selected memory cell from the precharge potential supplying line so that a potential of the one of plurality of bit lines changes depending on a potential held in the node; and

reading a change in potential of the one of the plurality of bit lines to read the potential held in the node of the selected memory cell.

6. The method for driving a semiconductor device, according to claim 5, wherein in the data reading period, other one of the plurality of source lines connected to a non-selected memory cell is connected to the precharge potential supplying line.

7. The method for driving a semiconductor device, according to claim 5, wherein the first transistor is a p-channel transistor.

8. The method for driving a semiconductor device, according to claim 5, wherein the first transistor is an n-channel transistor.

9. The method for driving a semiconductor device, according to claim 5, wherein a channel formation region of the second transistor includes an oxide semiconductor.

10. A method for driving a semiconductor device,

the semiconductor device comprising a memory cell array comprising a plurality of bit lines, at least one source line, a plurality of capacitor lines, and a plurality of memory cells,

wherein in one of the plurality of memory cells, a source electrode of a first transistor is electrically connected to one of the plurality of bit lines, a drain electrode of the first transistor is electrically connected to the source line, a gate electrode of the first transistor, a drain electrode of a second transistor, and one electrode of a capacitor are electrically connected to each other, the other electrode of the capacitor is electrically connected to one of the plurality of capacitor lines, and a node where a potential supplied from the one of the plurality of bit lines is held is formed between the gate electrode of the first transistor, the drain electrode of the second transistor, and the one electrode of the capacitor,

the method comprising the steps of, in a data reading period:

supplying a ground potential to one of the plurality of capacitor lines which is electrically connected to one of the plurality of memory cells, so that the one of the plurality of memory cells is to be selected;

supplying a ground potential to the source line;

electrically connecting one of the plurality of bit lines to a precharge potential supplying line so that the one of the plurality of bit lines is set to a precharge potential;

disconnecting the one of the plurality of bit lines of the selected memory cell from the precharge potential supplying line so that a potential of the one of plurality of bit lines changes depending on a potential held in the node; and

reading a change in potential of the one of the plurality of bit lines to read the potential held in the node of the selected memory cell.

11. The method for driving a semiconductor device, according to claim 10, wherein in the data reading period, a source line connected to a non-selected memory cell is connected to the precharge potential supplying line.

12. The method for driving a semiconductor device, according to claim 10, wherein the first transistor is a p-channel transistor.

13. The method for driving a semiconductor device, according to claim 10, wherein the first transistor is an n-channel transistor.

14. The method for driving a semiconductor device, according to claim 10, wherein a channel formation region of the second transistor includes an oxide semiconductor.