Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device, comprising:
- a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor;
a word line connected to both a gate of the first memory cell and a gate of the second memory cell;
a first line connected to a gate of the first transistor;
a second line connected to a gate of the second transistor; and
a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the bit line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage.
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Accused Products
Abstract
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
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Citations
20 Claims
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1. A nonvolatile semiconductor memory device, comprising:
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a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; a second line connected to a gate of the second transistor; and a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the bit line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A nonvolatile semiconductor memory device, comprising:
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a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string including a plurality of memory cells, the plurality of memory cells being stacked above a semiconductor substrate, the first memory string being connected to a first bit line, the second memory string being connected to a second bit line, both the first memory string and the second memory string being connected to a source line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; a second line connected to a gate of the second transistor; and a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the source line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of erasing data in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:
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a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; and a second line connected to a gate of the second transistor, the method comprising; applying a first voltage to the bit line; applying a second voltage to the first line; and applying a third voltage to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage. - View Dependent Claims (16, 17)
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18. A method of erasing data in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:
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a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string including a plurality of memory cells, the plurality of memory cells being stacked above a semiconductor substrate, the first memory string being connected to a first bit line, the second memory string being connected to a second bit line, both the first memory string and the second memory string being connected to a source line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor; a word line connected to both a gate of the first memory cell and a gate of the second memory cell; a first line connected to a gate of the first transistor; and a second line connected to a gate of the second transistor, the method comprising; applying a first voltage to the source line; applying a second voltage to the first line; and applying a third voltage to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage. - View Dependent Claims (19, 20)
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Specification