Nonvolatile semiconductor memory device

• US 8,649,227 B2
• Filed: 08/20/2013
• Issued: 02/11/2014
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maeda, Takashi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/970,689
• Publication Number:
  US 20130336064A1
• Time in Patent Office: 175 Days
• Field of Search: 365/188.29, 365/185.18, 365/185.17, 365/189.07
• US Class Current: 365/185.29
• CPC Class Codes: B60L 53/38 specially adapted for charging by inductive energy transfer
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/16 Flash programming of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H02J 2310/48 for electric vehicles [EV] or hybrid vehicles [HEV]
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor;

a word line connected to both a gate of the first memory cell and a gate of the second memory cell;

a first line connected to a gate of the first transistor;

a second line connected to a gate of the second transistor; and

a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the bit line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein the second voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the second voltage.

3. The nonvolatile semiconductor memory device according to claim 2,

wherein the third voltage is set so as not to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage.

4. The nonvolatile semiconductor memory device according to claim 1,

wherein the control circuit is configured to perform the erase operation on a condition that a fourth voltage is applied to the word line, the fourth voltage being lower than the second voltage.

5. The nonvolatile semiconductor memory device according to claim 1,

wherein one end of the first transistor is connected to the bit line, the other end of the first transistor is connected to the first memory cell, one end of the second transistor is connected to the bit line and the other end of the second transistor is connected to the second memory cell.

6. The nonvolatile semiconductor memory device according to claim 1, wherein

the first memory string further includes a third transistor,

the second memory string further includes a fourth transistor,

one end of the first transistor is connected to the bit line, the other end of the first transistor is connected to one end of the third transistor,

the other end of the third transistor is connected to the first memory cell,

one end of the second transistor is connected to the bit line,

the other end of the second transistor is connected to one end of the fourth transistor,

the other end of the fourth transistor is connected to the second memory cell.

7. The nonvolatile semiconductor memory device according to claim 6, further comprising:

a third line connected to a gate of the third transistor; and

a fourth line connected to a gate of the fourth transistor,

wherein the control circuit is configured to perform the erase operation on a condition that a fourth voltage is applied to the word line, a fifth voltage is applied to the third line and a sixth voltage is applied to the fourth line, the fourth voltage being lower than the second voltage, both the fifth voltage and the sixth voltage being lower than either the first voltage or the third voltage, both the fifth voltage and the sixth voltage being higher than the fourth voltage.

8. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string including a plurality of memory cells, the plurality of memory cells being stacked above a semiconductor substrate, the first memory string being connected to a first bit line, the second memory string being connected to a second bit line, both the first memory string and the second memory string being connected to a source line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor;

a word line connected to both a gate of the first memory cell and a gate of the second memory cell;

a first line connected to a gate of the first transistor;

a second line connected to a gate of the second transistor; and

a control circuit configured to perform an erase operation on a condition that a first voltage is applied to the source line, a second voltage is applied to the first line and a third voltage is applied to the second line, the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage.

9. The nonvolatile semiconductor memory device according to claim 8,

wherein the second voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the second voltage.

10. The nonvolatile semiconductor memory device according to claim 9,

wherein the third voltage is set so as not to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage.

11. The nonvolatile semiconductor memory device according to claim 8,

wherein the control circuit is configured to perform the erase operation on a condition that a fourth voltage is applied to the word line, the fourth voltage being lower than the second voltage.

12. The nonvolatile semiconductor memory device according to claim 8,

wherein one end of the first transistor is connected to the source line, the other end of the first transistor is connected to the first memory cell, one end of the second transistor is connected to the source line and the other end of the second transistor is connected to the second memory cell.

13. The nonvolatile semiconductor memory device according to claim 8, wherein

the first memory string further includes a third transistor,

the second memory string further includes a fourth transistor,

one end of the first transistor is connected to the source line, the other end of the first transistor is connected to one end of the third transistor,

the other end of the third transistor is connected to the first memory cell,

one end of the second transistor is connected to the source line,

the other end of the second transistor is connected to one end of the fourth transistor,

the other end of the fourth transistor is connected to the second memory cell.

14. The nonvolatile semiconductor memory device according to claim 13, further comprising:

a third line connected to a gate of the third transistor; and

a fourth line connected to a gate of the fourth transistor,

wherein the control circuit is configured to perform the erase operation on a condition that a fourth voltage is applied to the word line, a fifth voltage is applied to the third line and a six voltage is applied to the fourth line, the fourth voltage being lower than the second voltage, both the fifth voltage and the sixth voltage being lower than either the first voltage or the third voltage, both the fifth voltage and the sixth voltage being higher than the fourth voltage.

15. A method of erasing data in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:

a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string being commonly connected to a bit line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor;

a word line connected to both a gate of the first memory cell and a gate of the second memory cell;

a first line connected to a gate of the first transistor; and

a second line connected to a gate of the second transistor,

the method comprising;

applying a first voltage to the bit line;

applying a second voltage to the first line; and

applying a third voltage to the second line,

the first voltage and the third voltage being higher than the second voltage,

the first voltage being substantially same as the third voltage.

16. The method according to claim 15, wherein

the first memory string further includes a third transistor,

the second memory string further includes a fourth transistor,

one end of the first transistor is connected to the bit line, the other end of the first transistor is connected to one end of the third transistor,

the other end of the third transistor is connected to the first memory cell,

one end of the second transistor is connected to the bit line,

the other end of the second transistor is connected to one end of the fourth transistor,

the other end of the fourth transistor is connected to the second memory cell.

17. The method according to claim 16, wherein

the nonvolatile semiconductor memory device further comprises:

a third line connected to a gate of the third transistor; and

a fourth line connected to a gate of the fourth transistor,

the method further comprising;

applying fourth voltage to the word line;

applying a fifth voltage to the third line; and

applying a six voltage to the fourth line,

the fourth voltage being lower than the second voltage,

both the fifth voltage and the sixth voltage being lower than either the first voltage or the third voltage,

both the fifth voltage and the sixth voltage being higher than the fourth voltage.

18. A method of erasing data in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:

a memory cell array including a memory block, the block including a first memory string and a second memory string, the first memory string and the second memory string including a plurality of memory cells, the plurality of memory cells being stacked above a semiconductor substrate, the first memory string being connected to a first bit line, the second memory string being connected to a second bit line, both the first memory string and the second memory string being connected to a source line, the first memory string including a first memory cell and a first transistor, the second memory string including a second memory cell and a second transistor;

a word line connected to both a gate of the first memory cell and a gate of the second memory cell;

a first line connected to a gate of the first transistor; and

a second line connected to a gate of the second transistor,

the method comprising;

applying a first voltage to the source line;

applying a second voltage to the first line; and

applying a third voltage to the second line,

the first voltage and the third voltage being higher than the second voltage, the first voltage being substantially same as the third voltage.

19. The method according to claim 18, wherein

the first memory string further includes a third transistor,

the second memory string further includes a fourth transistor,

one end of the first transistor is connected to the source line, the other end of the first transistor is connected to one end of the third transistor,

the other end of the third transistor is connected to the first memory cell,

one end of the second transistor is connected to the source line,

the other end of the second transistor is connected to one end of the fourth transistor,

the other end of the fourth transistor is connected to the second memory cell.

20. The method according to claim 19, wherein

the nonvolatile semiconductor memory device further comprises:

a third line connected to a gate of the third transistor; and

a fourth line connected to a gate of the fourth transistor;

wherein the method comprises;

applying a fourth voltage to the word line;

applying a fifth voltage to the third line; and

applying a sixth voltage to the fourth line,

the fourth voltage being lower than the second voltage, both the fifth voltage and the sixth voltage being lower than either the first voltage or the third voltage, both the fifth voltage and the sixth voltage being higher than the fourth voltage.