High-rate interpolation or decimation filter in integrated circuit device

• US 8,650,236 B1
• Filed: 08/04/2009
• Issued: 02/11/2014
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chou, Shin-I
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Phan, Dean
• Application Number:
  US12/535,133
• Time in Patent Office: 1,652 Days
• Field of Search: 708/313
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0275 comprising non-recursive filters
• CPC Class Codes: H03H 17/0621 with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
• CPC Class Codes: H03H 2017/0247 Parallel structures using a slower clock
• CPC Class Codes: H03H 2017/0298 DSP implementation

Abstract

On a device having a maximum data rate, an interpolation filter can be configured in stages, with each stage may be broken into subfilters, which divides the output into phases. The ratio of the number of subfilters or phases in the final stage to the number of subfilters or phases in the initial stage is equal to the factor by which the data rate would otherwise increase. Thus for an interpolation factor of M, the output data rate can be kept the same as the input data rate by providing M subfilters, yielding M output phases each having an output rate equal to the input rate. The effective, or synthesized, output rate is M times the input rate. A decimation filter can be provided in the same way, with the effective input rate M times the output rate, even where the effective input rate would exceed the maximum data rate.

Claims

1. A FIR (Finite Impulse Response) filter structure on an integrated circuit device, for processing data samples and a set of coefficients, at an effective filter data rate that exceeds an input/output data rate by a factor, said FIR filter structure comprising:

a plurality of FIR filter stages including at a least an initial filter stage and a final filter stage, each of said filter stages having one or more subfilters defined by a subset of said set of coefficients, a first one of said initial and final filter stages having a number of subfilters that exceeds a number of subfilters in a second of said initial and final filter stages by said factor;

wherein;

each subfilter in each respective filter stage convolves input data with a respective subset of said set of coefficients; and

in at least one particular stage, at least a first subfilter in said particular stage includes a plurality of decomposed filters in a first filter order representing said respective subset of said set of coefficients in a first coefficient order, and at least a second subfilter in said particular stage includes said plurality of decomposed filters in a second filter order, different from said first filter order, representing said respective subset of said set of coefficients in a second coefficient order different from said first coefficient order.

2. The filter structure of claim 1 wherein:

said filter structure is an interpolation filter;

said first one of said initial and final filter stages is said final filter stage;

said effective filter data rate is an output rate; and

said input/output data rate is an input data rate.

3. The filter structure of claim 1 wherein:

said filter structure is a decimation filter;

said first one of said initial and final filter stages is said initial filter stage;

said effective filter data rate is an input rate; and

said input/output data rate is an output data rate.

4. The FIR filter structure of claim 1 further comprising at least one intermediate filter stage.

5. The FIR filter structure of claim 1 wherein:

said integrated circuit device has a maximum device data rate; and

said effective filter data rate exceeds said maximum device data rate.

6. The filter structure of claim 1 wherein a particular one of said decomposed filters in said at least a first subfilter is delayed relative to said particular one of said decomposed filters in said at least a second subfilter.

7. A method of programmably configuring a programmable integrated circuit device, having a maximum device data rate, as a FIR (Finite Impulse Response) filter structure, for processing data samples and a set of a number of coefficients, at an effective filter data rate that exceeds an input/output data rate by a factor, said method comprising:

programmably configuring logic of said programmable integrated circuit device as a plurality of FIR filter stages including at a least an initial filter stage and a final filter stage, each of said filter stages having one or more subfilters defined by a subset of said set of coefficients, a first one of said initial and final filter stages having a number of subfilters that exceeds a number of subfilters in a second of said initial and final filter stages by said factor;

programmably configuring each subfilter in each respective filter stage to convolve input data with a respective subset of said set of coefficients; and

programmably configuring, in at least one particular stage, at least a first subfilter in said particular stage to include a plurality of decomposed filters in a first filter order representing said respective subset of said set of coefficients in a first coefficient order, and at least a second subfilter in said particular stage to include said plurality of decomposed filters in a second filter order, different from said first filter order representing said respective subset of said set of coefficients in a second coefficient order.

8. The method of claim 7 wherein said filter structure is an interpolation filter;

said first one of said initial and final filter stages is said final filter stage;

said effective filter data rate is an output rate; and

said input/output data rate is an input data rate.

9. The method of claim 7 wherein said filter structure is a decimation filter;

said first one of said initial and final filter stages is said initial filter stage;

said effective filter data rate is an input rate; and

said input/output data rate is an output data rate.

10. The method of claim 7 further comprising programmably configuring logic of said programmable integrated circuit device as at least one intermediate filter stage.

11. The method of claim 7 wherein:

said effective filter data rate exceeds said maximum device data rate.

12. The method of claim 7 further comprising programmably configuring a particular one of said decomposed filters in said at least a first subfilter to be delayed relative to said particular one of said decomposed filters in said at least a second subfilter.

13. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for performing a method of programmably configuring a programmable integrated circuit device, having a maximum device data rate, as a FIR (Finite Impulse Response) filter structure, for processing data samples and a set of a number of coefficients, at an effective filter data rate that exceeds an input/output data rate by a factor, said instructions comprising:

instructions for programmably configuring logic of said programmable integrated circuit device as a plurality of FIR filter stages including at a least an initial filter stage and a final filter stage, each of said filter stages having one or more subfilters defined by a subset of said set of coefficients, a first one of said initial and final filter stages having a number of subfilters that exceeds a number of subfilters in a second of said initial and final filter stages by said factor;

instructions for programmably configuring each subfilter in each respective filter stage to convolve input data with a respective subset of said set of coefficients; and

instructions for programmably configuring, in at least one particular stage, at least a first subfilter in said particular stage to include a plurality of decomposed filters in a first filter order representing said respective subset of said set of coefficients in a first coefficient order, and at least a second subfilter in said particular stage to include said plurality of decomposed filters in a second filter order, different from said first filter order representing said respective subset of said set of coefficients in a second coefficient order.

14. The non-transitory machine-readable data storage medium of claim 13 wherein said instructions comprise instructions to configure said filter structure as an interpolation filter in which:

said first one of said initial and final filter stages is said final filter stage;

said effective filter data rate is an output rate; and

said input/output data rate is an input data rate.

15. The non-transitory machine-readable data storage medium of claim 13 wherein said instructions comprise instructions to configure said initial filter stage said filter structure as a decimation filter in which:

said first one of said initial and final filter stages is said initial filter stage;

said effective filter data rate is an input rate; and

said input/output data rate is an output data rate.

16. The non-transitory machine-readable data storage medium of claim 13 wherein said instructions comprise instructions to configure said filter such that said effective filter data rate exceeds said maximum device data rate.

17. The non-transitory machine-readable data storage medium of claim 13 further comprising instructions for programmably configuring a particular one of said decomposed filters in said at least a first subfilter to be delayed relative to said particular one of said decomposed filters in said at least a second subfilter.