Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer
First Claim
1. A method of fencing direct memory access (‘
- DMA’
) data transfers in a parallel active messaging interface (‘
PAMI’
) of a parallel computer, the parallel computer comprising a plurality of compute nodes that execute a parallel application, the PAMI comprising data communications endpoints, the compute nodes and the endpoints coupled for data communications through the PAMI and through data communications resources including DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, in the same order in which the communications are transmitted, the method comprising;
initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, an origin endpoint and a target endpoint, each DMA instruction effecting a deterministic DMA data transfer through a DMA controller and a segment of shared memory in which the DMA data transfers are effected according to the ordered sequence of the DMA instructions; and
executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.
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Accused Products
Abstract
Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.
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Citations
18 Claims
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1. A method of fencing direct memory access (‘
- DMA’
) data transfers in a parallel active messaging interface (‘
PAMI’
) of a parallel computer, the parallel computer comprising a plurality of compute nodes that execute a parallel application, the PAMI comprising data communications endpoints, the compute nodes and the endpoints coupled for data communications through the PAMI and through data communications resources including DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, in the same order in which the communications are transmitted, the method comprising;initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, an origin endpoint and a target endpoint, each DMA instruction effecting a deterministic DMA data transfer through a DMA controller and a segment of shared memory in which the DMA data transfers are effected according to the ordered sequence of the DMA instructions; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints. - View Dependent Claims (2, 3, 4, 5, 6)
- DMA’
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7. A parallel computer that fences direct memory access (‘
- DMA’
) data transfers in a parallel active messaging interface (‘
PAMI’
), the parallel computer comprising a plurality of compute nodes that execute a parallel application, the PAMI comprising data communications endpoints on the compute nodes of the parallel computer, the compute nodes and the endpoints coupled for data communications through the PAMI and through data communications resources including DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, in the same order in which the communications are transmitted, the compute nodes comprising computer processors operatively coupled to computer memory having disposed within it computer program instructions that, when executed by the computer processors, cause the parallel computer to function by;initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, an origin endpoint and a target endpoint, each DMA instruction effecting a deterministic DMA data transfer through a DMA controller and a segment of shared memory in which the DMA data transfers are effected according to the ordered sequence of the DMA instructions; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints. - View Dependent Claims (8, 9, 10, 11, 12)
- DMA’
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13. A computer program product for fencing direct memory access (‘
- DMA’
) data transfers in a parallel active messaging interface (‘
PAMI’
) of a parallel computer, the parallel computer comprising a plurality of compute nodes that execute a parallel application, the PAMI comprising data communications endpoints on the compute nodes of the parallel computer, the compute nodes and the endpoints coupled for data communications through the PAMI and through data communications resources including DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, in the same order in which the communications are transmitted, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when installed and executed, cause the parallel computer to function by;initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, an origin endpoint and a target endpoint, each DMA instruction effecting a deterministic DMA data transfer through a DMA controller and a segment of shared memory in which the DMA data transfers are effected according to the ordered sequence of the DMA instructions; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints. - View Dependent Claims (14, 15, 16, 17, 18)
- DMA’
Specification