Capacitor save energy verification

• US 8,650,363 B2
• Filed: 05/27/2012
• Issued: 02/11/2014
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Inventors: Sartore, Ronald H
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US13/481,845
• Publication Number:
  US 20130111109A1
• Time in Patent Office: 625 Days
• Field of Search: 711/113, 711/119, 711/135, 711/162, 711/165, 714/14, 714/22, 714/24
• US Class Current: 711/135
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 11/1458 Management of the backup or restore process
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Claims

1. A memory subsystem configured to obtain power from an external system and from at least one power capacitor, comprising:

circuits embodying logic to verify a power delivery capability of the at least one power capacitor; and

circuits embodying logic to measure an ending voltage of the at least one capacitor at an end of an uninterrupted data backup operation from a volatile to a nonvolatile memory, and to determine if the ending voltage is within a sufficient voltage margin to reliably complete a next data backup from the volatile to the nonvolatile memory.

2. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to time at least one of a charge and discharge rate of the at least one capacitor using a predetermined load and voltage.

3. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to apply one or more of an operating temperature, operating voltage, and component age to capacitor power verification.

4. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to apply prior operational behavior of the at least one capacitor to capacitor power verification.

5. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to verify, upon restoration of external system power, that the at least one power capacitor has sufficient power to enable the data backup.

6. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to verify, after a time interval has passed, that the at least one power capacitor has sufficient power to enable the data backup.

7. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitor further comprises:

logic to verify, in response to a signal from the external system, that the at least one power capacitor has sufficient power to enable the data backup.

8. The memory subsystem of claim 1, further comprising:

logic to signal the external system of a result of power verification of the at least one capacitor.

9. A method of verifying the power delivery capability of at least one power capacitor in a memory subsystem, comprising:

performing a data backup from a volatile to a nonvolatile memory; and

verifying a power delivery capability of the at least one power capacitor, by measuring an ending voltage of the at least one capacitor at an end of an uninterrupted data backup operation from the volatile to a nonvolatile memory, and to determine if the ending voltage is within a sufficient voltage margin to reliably complete a next data backup from the volatile to the nonvolatile memory.

10. The method of claim 9, wherein verifying a power delivery capability of the at least one power capacitor further comprises:

timing at least one of a charge and discharge rate of the at least one capacitor using a predetermined load and voltage.

11. A device comprising:

a memory subsystem configured to obtain power from the device and from at least one power capacitor;

circuits embodying logic to cause power from the at least one power capacitor to be directed to memory components of the memory subsystem after device power to the memory subsystem is discontinued; and

circuits embodying logic to verify a power delivery capability of the at least one power capacitor, by measuring an ending voltage of the at least one capacitor at an end of an uninterrupted data backup operation from a volatile to a nonvolatile memory, and to determine if the ending voltage is within a sufficient voltage margin to reliably complete a next data backup from the volatile to the nonvolatile memory.