Computer system and method of protection for the system's marking store

• US 8,650,437 B2
• Filed: 06/29/2010
• Issued: 02/11/2014
• Est. Priority Date: 06/29/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fry, Richard E., Gollub, Marc A., Lastras-Montano, Luis A., Retter, Eric E., Wright, Kenneth L.
• Primary Examiner(s): TRUONG, LOAN
• Application Number:
  US12/825,521
• Publication Number:
  US 20110320911A1
• Time in Patent Office: 1,323 Days
• Field of Search: 714/6.1, 714/6.24, 714/42, 714/52, 714/752, 714/758, 714/768
• US Class Current: 714/6.24
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.

Claims

1. A method for protection of a computer system'"'"'s marking store, comprising the steps of executing a plurality of reading and writing processor operations for data processing by a computer system having a plurality of core processors and a marking store for a memory controller with hardware and firmware control, including

writing in a processor operation of a processor of computer system to said computer system'"'"'s marking store with a slow Error Correcting Code (ECC) decoder, and continuing during said processor operations said data processing, and reading from marking store data with a read operation said computer system'"'"'s marking store with a fast ECC decoder during said data processing by said processor operations, and

notifying said memory controller firmware control when the computer system'"'"'s marking store has been updated to lock writing to the computer system'"'"'s marking store until controller firmware has read any updates of the computer system'"'"'s marking store during said data processing of said processor operations;

wherein said computer system'"'"'s marking store which is written by said slow ECC decoder, and read by said fast ECC decoder for every read operation is protected with a locking mechanism allowing said hardware control continuous access to the marking store and allows for said memory controller firmware control to be notified if the marking store has been updated and which locking mechanism guarantees that controller firmware cannot write to the marking store until the controller firmware has read any updates.

2. The method for protection of a computer system'"'"'s marking store according to claim 1

wherein said computer system'"'"'s marking store which is written by said slow ECC decoder, and read by said fast ECC decoder for every read operation is protected with a locking mechanism allowing said hardware control continuous access to the marking store and allows for said memory controller firmware control to be notified if the marking store has been updated and which locking mechanism guarantees that controller firmware cannot write to the marking store until the controller firmware has read any updates.

3. The method for protection of a computer system'"'"'s marking store according to claim 2 wherein the hardware control includes hardware marking for said memory controller and a value read from said marking store is set to a defined value when there is a parity error detected by said slow ECC decoder.

4. The method for protection of a computer system'"'"'s marking store according to claim 3, such that said slow ECC decoder for said computer system'"'"'s marking store which assumes there is not a mark placed is able to recalculate a mark value which is written and said mark value can be placed back in the mark store with good parity.

5. The method for protection of a computer system'"'"'s marking store according to claim 4, wherein said hardware marking applies chip marks, and a work around is implemented for hardware bugs which interact with the marking process allowing computer system firmware (FW) to alter or block marks before the hardware (HW) marking is applied.

6. The method for protection of a computer system'"'"'s marking store according to claim 5, automatic mark store updates are disabled by updating an unused mark store address register entry in said marking store with an updated mark data value generated by said slow ECC decoder when the slow ECC decoder has found a valid mark, and the firmware (FW) is notified that the mark store has been updated with the updated mark value.

7. The method for protection of a computer system'"'"'s marking store according to claim 6, wherein, thereafter, said updated mark value is used to correct data currently being processed by said slow ECC decoder.

8. The method for protection of a computer system'"'"'s marking store according to claim 7, wherein a mark store entry associated with a rank being decoded is not updated when the updated mark store address register value is updated, and said slow ECC decoder continues to use the not updated mark data associated with the rank for data correction for future read ops to the rank.

9. The method for protection of a computer system'"'"'s marking store according to claim 8, wherein after the firmware (FW) has been notified that mark store address register entry has been updated, the firmware can read out the updated mark value and apply it to a memory rank in which an error occurred which is known from an address of the mark store entry associated with a rank being decoded is not updated, or generates the firmware'"'"'s own mark update.

10. The method for protection of a computer system'"'"'s marking store according to claim 9, wherein after there has been a firmware mark update, the firmware can also see a mark value computed by the hardware.

11. A computer system, comprising:

a Central Electronic Complex (CEC) having a plurality of core processors for said computer system which are coupled by an L3 eDRAM cache and interconnect bus of said CEC to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store, said CEC having SMP Links and Remote SMP Links for connection of the core processors to other system elements, each of said dual-channel DDR3 memory controllers with loaded firmware having a 4-byte/rank mark store protected by one sense parity bit for marking data associated with each memory rank which is read and written by firmware through scan communication, said loaded firmware of said memory controllers being responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing a marking store hardware to time out.

12. The computer system of claim 11, wherein said marking store has a mark store address register storing values therein to indicate when a hardware update to the marking store has occurred before the marking store firmware has read all of said marking store.

13. The computer system of claim 12, wherein said marking store has status hardware bits indicating when there is a read in progress, when read by scan communication, when set/reset by scan communication and when reset by hardware.

14. The computer system of claim 13, wherein said marking store address register is set by marking store hardware when updated by an ECC decoder of said ECC decoder control and prevents firmware mark updates from overwriting a hardware mark update.

15. The computer system according to claim 14, wherein said mark attention register'"'"'s setting is used when a hardware mark has occurred.

16. The computer system according to claim 15, wherein when said mark attention register'"'"'s setting is set a scan communication writes to said marking store'"'"'s mark store address register and a store is inhibited.

17. A method of controlling marking store updates in a central electronic complex, comprising the steps of

updating a marking store making an entry as an unused mark store address entry with an updated mark data value generated by an Error Correcting Code (ECC) slow decoder when said ECC slow decoder has found a valid mark and notifying marking store firmware that said marking store has been updated,

using said updated mark data value to correct data currently being processed by said ECC slow decoder but not marking a mark store entry associated with a memory rank being decoded that has not been updated,

after said marking store firmware has been notified that marking store has been updated, either reading out the updated mark data value and applying said updated mark value to the rank in which an error occurred, when known from an error address associated with the memory rank, or generating a mark update for said marking store;

and

continuing to use the mark data associated with said memory rank for data correction for future read operations to said memory rank.

18. The method of controlling marking store updates in a central electronic complex according to claim 17, further comprising the steps of protecting a content of marking store register files by a single parity bit covering a 4-bytes of marking information per memory rank entry, said parity being generated when data is written to said marking store by firmware or by said ECC slow decoder) and checking said parity by a fast ECC fast decoder.

19. The method of controlling marking store updates in a central electronic complex according to claim 17, further comprising the steps of, if a mark store parity error is detected by the fast ECC decoder, setting a Finite Impulse Response (FIR) bit and forcing mark data read from the marking store to zero, for a current read operation only, by a fast ECC decoder to provide for recovery of a mark store parity error through a re-write of mark data by firmware or hardware.