Management of a non-volatile memory based on test quality

• US 8,650,446 B2
• Filed: 03/24/2010
• Issued: 02/11/2014
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Byom, Matthew, Wakrat, Nir J., Herman, Kenneth, Post, Daniel J.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/730,551
• Publication Number:
  US 20110239064A1
• Time in Patent Office: 1,420 Days
• Field of Search: 714/718, 714/723, 714/763
• US Class Current: 714/723
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. The NVM may be managed based on results of a test performed on the NVM. The test may indicate, for example, physical memory locations that may be susceptible to errors, such as certain pages in the blocks of the NVM. Tests on multiple NVMs of the same type may be compiled to create a profile of error tendencies for that type of NVM. In some embodiments, data may be stored in the NVM based on individual test results for the NVM or based on a profile of the NVM type. For example, memory locations susceptible to error may be retired or data stored in those memory locations may be protected by a stronger error correcting code.

Claims

1. A method of configuring a memory system comprising a non-volatile flash memory, the method comprising:

performing a test on a plurality of physical memory locations in a flash non-volatile memory, wherein the flash non-volatile memory comprises multiple dies, each die comprises a plurality of blocks and each block comprises a plurality of pages, and wherein results of the test indicate which of the physical memory locations failed the test;

identifying, from the results, a pattern of physical memory locations tending to fail the test, wherein the pattern shows at least one page number common to each block of at least one die that includes a percentage of same page failures that exceeds a predetermined threshold; and

managing the physical memory locations of the non-volatile memory based on the pattern.

2. The method of claim 1, wherein the test is performed during a manufacturing process of the memory system.

3. The method of claim 1, Wherein the managing comprises configuring the memory system to access the non-volatile memory based on the pattern.

4. The memory system of claim 3, wherein the configuring is performed during a manufacturing process of the memory system.

5. The method of claim 1, wherein the managing comprises configuring the memory system to store data in the non-volatile memory based on the pattern.

6. The method of claim 5, wherein the configuring comprises at least one of:

retiring at least a portion of the physical memory locations based on the pattern, applying error correction to data being stored in the non-volatile memory based on the pattern, determining a number of bits per cell to use for particular physical memory locations based on the pattern, and storing particular types of data at particular physical memory locations in the non-volatile memory based on the pattern.

7. The method of claim 1, wherein the non-volatile memory comprises flash memory.

8. A non-volatile Flash memory system, comprising:

at least one Flash die, each die comprises a plurality of blocks and each block comprises a plurality of pages; and

a controller operative to;

perform a test on the at least one Flash die, wherein results of the test indicate which pages failed the test;

identify, from the results, a pattern of persistent page failure across a predetermined number of blocks of the at least one die, wherein the pattern includes at least one page number common to each block that includes a percentage of same page failures that exceeds a predetermined threshold; and

manage the at least one Flash die based on the pattern.

9. The non-volatile Flash memory system of claim 8, wherein the persistent page failure corresponds to the same page in each block.

10. The non-volatile Flash memory system of claim 8, wherein the at least one die comprises a plurality of dies, wherein the persistent page failure corresponds to the same page of the same block in each die.

11. A non-volatile Flash memory system, comprising:

at least one Flash die, each die comprises a plurality of blocks and each block comprises a plurality of pages; and

a controller operative to;

perform a test on the at least one Flash die, wherein results of the test indicate which pages failed the test;

identify, from the results, a pattern of consistent failures across a predetermined number of blocks of the at least one die; and

manage the at least one Flash die based on the pattern such that blocks included in the pattern are managed as relatively lower level cell non-volatile memory and blocks not included in the pattern are managed as relatively higher level cell non-volatile memory.