Method for manufacturing a semiconductor device and semiconductor device

• US 8,652,906 B2
• Filed: 05/21/2013
• Issued: 02/18/2014
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin, Rieger, Walter, Zundel, Markus
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/899,101
• Publication Number:
  US 20130252423A1
• Time in Patent Office: 273 Days
• Field of Search: 438/259, 438270-274, 438/589, 438/E29.201
• US Class Current: 438/271
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate with an active region and a margin region adjacent to the active region, wherein the active region comprises trenches filled with conductive material in the semiconductor substrate; and

breaking through a spacer layer having varying thickness, in the margin region at a selected location and removing at least part of the spacer layer in the active region; and

selecting the location such that, on condition that the spacer layer in the active region is removed such that at least part of the semiconductor mesa structure is exposed and the conductive material in the trenches is not exposed, the spacer layer in the margin region is removed to the conductive layer and not to the semiconductor substrate.

2. The method of claim 1, wherein removing comprises anisotropic etching acting equally on the active region and the margin region.

3. The method of claim 2, wherein the etching comprises a combination of a chemical-mechanical polishing and an oxide etching or an oxide etching without any chemical-mechanical polishing.

4. The method of claim 1, comprising performing a trench etching in the semiconductor mesa structure after the breaking through, without covering the location in the margin region.

5. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate with an active region and a margin region adjacent to the active region, wherein the active region comprises trenches filled with conductive material in the semiconductor substrate, wherein the conductive material in the trenches is insulated from the semiconductor substrate by an insulation layer, and wherein a semiconductor mesa structure is formed between each two trenches, wherein a layer of the conductive material, insulated from the semiconductor substrate by an insulation layer and short-circuited with the conductive material in the trenches, is formed in the margin region, and wherein a spacer layer comprising a varying thickness in the margin region is formed over the semiconductor substrate; and

breaking through the spacer layer in the margin region at a selected location and removing at least part of the spacer layer in the active region, using a common process,

wherein the location is selected such that, on condition that the spacer layer in the active region is removed such that at least part of the semiconductor mesa structure is exposed and the conductive material in the trenches is not exposed, the spacer layer in the margin region is removed to the conductive layer and not to the semiconductor substrate.

6. The method of claim 5, wherein the common process comprises anisotropic etching acting equally on the active region and the margin region.

7. The method of claim 6, wherein the etching comprises a combination of a chemical-mechanical polishing and an oxide etching or an oxide etching without any chemical-mechanical polishing.

8. The method of claim 5, comprising performing a trench etching in the semiconductor mesa structure after the breaking through, without covering the location in the margin region.

9. The method of claim 5, comprising metalizing the active region and the margin region after the breaking through and a resulting metallization layer is subsequently patterned to separate a contact of the active region from a contact of the margin region.

10. The method of claim 5, wherein the spacer layer comprises a material which becomes more liquid with increasing temperature and in which the spacer layer is deposited at a temperature at which the material is so liquid that it diffuses into a dimple or acquires a thickness decreasing towards an edge.

11. The method of claim 5, comprising patterning the contact layer in the margin region such that it comprises an edge at which the contact layer stops, wherein the spacer layer comprises, over the contact layer, a thickness decreasing towards the edge, and wherein the location is selected near the edge so that the spacer layer is removed to the contact layer in the common process.

12. The method of claim 5, wherein the contact layer in the margin region comprises at least two adjacent traces spaced apart from each other, wherein the spacer layer comprises a thickness decreasing over the one trace in the direction of the other trace and decreasing over the other trace in the direction of the one trace, transversely to the adjacent traces, and in which the location comprises a continuous region including part of the one trace, a gap between the traces and a bordering part of the other trace.

13. The method of claim 5, comprising:

forming a trench under the contact layer in the margin region; and

selecting the location such that it extends over the trench.