Semiconductor device and method for manufacturing the same

• US 8,653,520 B2
• Filed: 02/04/2011
• Issued: 02/18/2014
• Est. Priority Date: 02/12/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Fujii, Teruyuki, Sasagawa, Shinya, Kurata, Motomu, Imahayashi, Ryota, Taguchi, Fumika
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US13/021,343
• Publication Number:
  US 20120074407A1
• Time in Patent Office: 1,110 Days
• Field of Search: 257/57, 438/152
• US Class Current: 257/57
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.

Claims

1. A semiconductor device comprising

a first transistor;

an insulating layer over the first transistor; and

a second transistor over the insulating layer,

wherein the first transistor comprises;

a first channel formation region;

a first gate insulating layer provided over the first channel formation region;

a first gate electrode overlapping with the first channel formation region, over the first gate insulating layer; and

a first source electrode electrically connected to the first channel formation region and a first drain electrode electrically connected to the first channel formation region,

wherein the second transistor comprises;

a second channel formation region including an oxide semiconductor;

a second source electrode electrically connected to the second channel formation region and a second drain electrode electrically connected to the second channel formation region;

a second gate electrode overlapping with the second channel formation region; and

a second gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm, and

wherein a top surface of the first gate electrode is aligned with the surface of the insulating layer.

2. The semiconductor device according to claim 1,

wherein the top surface of the first gate electrode is exposed to be included in a same surface as the insulating layer, and

wherein the first gate electrode and the second source electrode or the second drain electrode are in contact with each other on the top surface of the first gate electrode.

3. The semiconductor device according to claim 1, wherein the surface of the insulating layer is formed through a CMP treatment.

4. The semiconductor device according to claim 1, further comprising impurity regions with the first channel formation region provided therebetween.

5. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistance, an electronic book, a mobile phone, a camera and a television device.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode overlapping with the first channel formation region over the first gate insulating layer, a first source electrode layer electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;

forming an insulating layer over the first transistor;

planarizing the insulating layer so that a surface of the insulating layer has a root-mean-square surface roughness of less than or equal to 1 nm; and

forming a second transistor including a second channel formation region including an oxide semiconductor, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode overlapping with the second channel formation region, and a gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the second channel formation region including the oxide semiconductor is in contact with the insulating layer, and

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein a top surface of the first gate electrode is aligned with the surface of the insulating layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the second channel formation region is formed over the surface of the insulating layer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistance, an electronic book, a mobile phone, a camera and a television device.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode which overlaps with the first channel formation region and is provided over the first gate insulating layer, a first source electrode electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;

forming an insulating layer over the first transistor;

planarizing the insulating layer so that a surface of the insulating layer has a root-mean-square roughness of less than or equal to 1 nm and a top surface of the first gate electrode is exposed to be included in a same surface as the insulating layer; and

forming a second transistor including a second channel formation region including an oxide semiconductor over the insulating layer, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode provided to overlap with the second channel formation region, a second gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the second source electrode or the second drain electrode are provided to be in contact with the top surface of the first gate electrode, and

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the top surface of the first gate electrode is aligned with the surface of the insulating layer.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the second channel formation region is formed over the surface of the insulating layer.

13. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistance, an electronic book, a mobile phone, a camera and a television device.

14. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode overlapping with the first channel formation region over the first gate insulating layer, a first source electrode layer electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;

forming an insulating layer over the first transistor;

planarizing the insulating layer by a CMP treatment; and

forming a second transistor including a second channel formation region including an oxide semiconductor, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode overlapping with the second channel formation region, and a gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the second channel formation region including the oxide semiconductor is in contact with the insulating layer,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

15. The method for manufacturing a semiconductor device according to claim 14, wherein a top surface of the first gate electrode is aligned with a surface of the insulating layer.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the second channel formation region is formed over a surface of the insulating layer.

17. The method for manufacturing a semiconductor device according to claim 14, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistance, an electronic book, a mobile phone, a camera and a television device.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor including a first channel formation region, a first gate insulating layer provided over the first channel formation region, a first gate electrode which overlaps with the first channel formation region and is provided over the first gate insulating layer, a first source electrode electrically connected to the first channel formation region, and a first drain electrode electrically connected to the first channel formation region;

forming an insulating layer over the first transistor;

planarizing the insulating layer by a CMP treatment so that a top surface of the first gate electrode is exposed to be included in a same surface as the insulating layer; and

forming a second transistor including a second channel formation region including an oxide semiconductor over the insulating layer, a second source electrode electrically connected to the second channel formation region, a second drain electrode electrically connected to the second channel formation region, a second gate electrode provided to overlap with the second channel formation region, a second gate insulating layer provided between the second channel formation region and the second gate electrode,

wherein the second source electrode or the second drain electrode are provided to be in contact with the top surface of the first gate electrode, and

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the top surface of the first gate electrode is aligned with the surface of the insulating layer.

20. The method for manufacturing a semiconductor device according to claim 18, wherein the second channel formation region is formed over the surface of the insulating layer.

21. The method for manufacturing a semiconductor device according to claim 18, wherein the semiconductor device is incorporated in one selected from the group consisting of a computer, a personal digital assistance, an electronic book, a mobile phone, a camera and a television device.