Micro-interconnects for light-emitting diodes

• US 8,653,542 B2
• Filed: 01/13/2011
• Issued: 02/18/2014
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: TSMC Solid State Lighting Ltd. (Ennostar, Inc.)
• Inventors: Hsia, Hsing-Kuo, Yu, Chih-Kuang
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US13/005,731
• Publication Number:
  US 20120181568A1
• Time in Patent Office: 1,132 Days
• Field of Search: 257/99, 257/E33.056, 257/E33.064, 438/28
• US Class Current: 257/88
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/54 having a particular shape
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

The present disclosure provides a method of fabricating a light emitting diode (LED) package. The method includes bonding a plurality of separated light emitting diode (LED) dies to a substrate, wherein each of the plurality of separated LED dies includes an n-doped layer, a quantum well active layer, and a p-doped layer; depositing an isolation layer over the plurality of separated LED dies and the substrate; etching the isolation layer to form a plurality of via openings to expose portions of each LED die and portions of the substrate; forming electrical interconnects over the isolation layer and inside the plurality of via openings to electrically connect between one of the doped layers of each LED die and the substrate; and dicing the plurality of separated LED dies and the substrate into a plurality of LED packages.

Claims

1. A method of fabricating a plurality of light emitting diode (LED) packages, comprising:

bonding a plurality of separated LED dies to a substrate, wherein each of the plurality of separated LED dies includes an n-doped layer, a quantum well active layer, and a p-doped layer;

depositing an isolation layer conformally over the plurality of separated LED dies and the substrate;

etching the isolation layer to form a plurality of via openings to expose portions of each LED die and portions of the substrate;

forming electrical interconnects over the isolation layer and inside the plurality of via openings to electrically connect between one of the doped layers of each LED die and the substrate, wherein the etching and the forming the electrical interconnects are performed such that;

the exposed portions of one of the separated dies include a contact metallization;

the exposed portions of the substrate include a contact electrode disposed on the substrate; and

the contact metallization and the contact electrode are electrical interconnected; and

dicing the plurality of separated LED dies and the substrate into a plurality of LED packages.

2. The method of claim 1, wherein the bonding comprises bonding an electrode of one of the separated LED dies to a bonding contact disposed on the substrate.

3. The method of claim 1, wherein the substrate comprises a plurality of through silicon vias (TSVs), each of the plurality of TSVs being coupled with one of the n-doped layer and the p-doped layer, and wherein a subset of the plurality of TSVs are aligned with a subset of the via openings, respectively.

4. The method of claim 1, wherein the bonding comprises forming a thermal conductive path for transferring heat away from one of the separated LED dies.

5. The method of claim 1, wherein the bonding comprises bonding a carrier substrate of one of the separated LED dies to a bonding contact disposed on the substrate.

6. The method of claim 1, wherein the forming electrical interconnects comprises depositing an interconnect layer and filling the plurality of via openings with the interconnect layer to form a plurality of electrical vias to the exposed portions of each LED die and the exposed portions of the substrate.

7. The method of claim 6, wherein the depositing an interconnect layer comprises depositing a transparent conductive layer over the isolation layer and to fill the plurality of via openings with the transparent conductive layer.

8. The method of claim 1, further comprising forming a phosphor layer and a lens over each LED die after the forming electrical interconnects and before the dicing.

9. The method of claim 1, wherein the depositing the isolation layer is performed so that the isolation layer has a uniform thickness.

10. A method of fabricating a plurality of light emitting diode (LED) packages, comprising:

providing a plurality of separated LED dies, wherein each of the plurality of separated dies includes an n-doped layer, a quantum well active layer, a p-doped layer, and a p-contact metal layer on a carrier substrate;

bonding the carrier substrate of the plurality of separated LED dies to a packaging substrate, the packaging substrate including a through silicon via (TSV);

depositing an isolation layer over the plurality of separated LED dies and the packaging substrate;

etching the isolation layer to form a plurality of via openings to expose portions of each of the plurality of separated LED dies and portions of the packaging substrate, wherein at least one of the plurality of via openings is aligned with the TSV;

depositing an interconnect layer over the isolation layer and the plurality of via openings to form electrical interconnects between the n-doped layer of each of the plurality of separated LED dies and the packaging substrate;

forming a phosphor layer and a lens over each of the plurality of separated LED dies; and

dicing the plurality of separated LED dies and the packaging substrate into a plurality of LED packages.

11. The method of claim 10, wherein the bonding electrically connects the p-doped layer of the plurality of separated dies to the packaging substrate.

12. The method of claim 10, wherein the etching the isolation layer comprises forming a plurality of via openings to expose the n-doped layer of the plurality of separated dies.

13. The method of claim 10, wherein the depositing an interconnect layer comprises metal plating with a metal layer to fill the plurality of via openings and to form an electrical interconnection between the n-doped layer and an electrode on the packaging substrate.

14. The method of claim 10, wherein the depositing an interconnect layer comprises depositing a transparent conductive layer over the isolation layer and to fill the plurality of via openings to form an electrical interconnection between the n-doped layer and an electrode on the packaging substrate.

15. The method of claim 10, wherein the depositing the isolation layer is performed such that the isolation layer is deposited conformally over the plurality of separated LED dies.

16. A method, comprising:

providing a packaging substrate, the packaging substrate having a first side and a second side opposite the first side, wherein the packaging substrate includes a first pad and a second pad disposed over the first side and a third pad and a fourth pad disposed over the second side, and wherein the packaging substrate includes a first through silicon via (TSV) and a second TSV each extending from the first side to the second side, the first TSV electrically coupling the first pad to the third pad, and the second TSV electrically coupling the second pad to the fourth pad;

bonding a light-emitting diode (LED) die to the first pad, the LED die including an n-doped layer, a quantum well active layer, and a p-doped layer;

forming an isolation layer over the LED die and over the packaging substrate;

etching the isolation layer to form a first opening and a second opening in the isolation layer, the first opening exposing a portion of the LED die, the second opening exposing the second pad; and

depositing a conductive layer over the isolation layer, the conductive layer filling the first opening and the second opening, thereby electrically interconnecting the LED die and the second TSV.

17. The method of claim 16, wherein the forming the isolation layer is performed so that the isolation layer is formed conformally.

18. The method of claim 16, further comprising:

forming a phosphor layer and a lens over the LED die; and

thereafter dicing the packaging substrate.