Solid-state image capturing element and driving method for the same, method for manufacturing solid-state image capturing element, and electronic information device

• US 8,653,570 B2
• Filed: 04/09/2010
• Issued: 02/18/2014
• Est. Priority Date: 04/10/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Konishi, Takefumi
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/757,359
• Publication Number:
  US 20100259658A1
• Time in Patent Office: 1,411 Days
• Field of Search: 257290-294, 257431-448, 257/E31.073, 257/E31.127, 257/E27.133
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A solid-state image capturing element includes, disposed in a surface portion from an upper part of the photodiode region to the electric charge detecting section: a second conductivity type first region; a second conductivity type second region; and a second conductivity type third region, one end of which is adjacent to the second conductivity type second region and the other end of which is adjacent to the electric charge detecting section, where each impurity concentration of the first, second and third regions is set in a manner to form an electric field being directed from the second conductivity type first region through the second conductivity type second region to the second conductivity type third region.

Claims

1. A solid-state image capturing element, comprising, as a unit pixel section disposed in a semiconductor substrate:

a photodiode region including a first conductivity type semiconductor region constituting a photoelectric conversion and accumulation section for photoelectrically converting light into signal charges for electric charge accumulation, and a second conductivity type semiconductor pinning layer for separating the photoelectric conversion and accumulation section from a surface of the semiconductor substrate;

a gate electrode one end of which is adjacent to the second conductivity type semiconductor pinning layer, wherein one end portion of the gate electrode overlaps one end portion of the photoelectric conversion and accumulation section; and

an electric charge detecting section as a first conductivity type drain region adjacent to the other end of the transfer gate electrode,

the solid-state image capturing element further comprising, disposed in a surface portion from an upper part of the photodiode region to the electric charge detecting section;

a second conductivity type first region as the second conductivity type semiconductor pinning layer;

a second conductivity type second region, one end of which is adjacent to the second conductivity type first region and which is disposed in an overlapping region of the photoelectric conversion and accumulation section; and

a second conductivity type third region, one end of which is adjacent to the second conductivity type second region and the other end of which is adjacent to the electric charge detecting section,

wherein each impurity concentration of the first, second and third regions is set in a manner to form an electric field being directed from the second conductivity type first region through the second conductivity type second region to the second conductivity type third region,

the second conductivity type third region contacts only the first conductivity type semiconductor region and the second conductivity type second region along a linear boundary separating the second conductivity type third region from the first conductivity type semiconductor region and the second conductivity type second region, at the one end portion of the gate electrode, the linear boundary being perpendicular to the surface of the semiconductor substrate and extending along a portion of both the first conductivity type semiconductor region and the second conductivity type second region, and

the second conductivity type third region and the first conductivity type semiconductor region are formed within a first conductivity type semiconductor substrate.

2. A solid-state image capturing element according to claim 1, wherein

a relationship among an impurity concentration C1 of the second conductivity type first region, an impurity concentration C2 of the second conductivity type second region, and an impurity concentration C3 of the second conductivity type third region is set to be C1>

C2>

C3.

3. A solid-state image capturing element according to claim 2, wherein

the impurity concentration C1 of the second conductivity type first region is set to be 8×

10¹⁷ cm<sup>−

3</sup> to 3×

10¹⁸ cm<sup>−

3</sup>, the impurity concentration C2 of the second conductivity type second region is set to be 9×

10¹⁶ cm<sup>−

3</sup> to 5×

10¹⁷ cm<sup>−

3</sup>, and the impurity concentration C3 of the second conductivity type third region is set to be 3×

10¹⁶ cm<sup>−

3</sup> to 1×

10¹⁷ cm<sup>−

3</sup>.

4. A solid-state image capturing element according to claim 1, wherein

a relationship among a depth D1 of the second conductivity type first region from a substrate surface, a depth D2 of the second conductivity type second region from the substrate surface, and a depth D3 of the second conductivity type third region from the substrate surface is D3>

D1>

D2.

5. A solid-state image capturing element according to claim 1, wherein

the first conductivity type semiconductor region is completely buried inside the semiconductor substrate, in a state surrounded by the second conductivity type semiconductor pinning layer thereabove, the gate electrode adjacent to one end of the second conductivity type semiconductor pinning layer, a second conductivity type region adjacent to and extending below the other end portion of the second conductivity type semiconductor pinning layer, and a buried second conductivity type region adjacently below the second conductivity type region and disposed below the first conductivity type semiconductor region.

6. A solid-state image capturing element according to claim 1, wherein

the second conductivity type second region is adjacent to the second conductivity type first region and disposed on the overlapping region of the photoelectric conversion and accumulation section below the gate electrode.

7. A solid-state image capturing element according to claim 1, wherein

a boundary between the second conductivity type first region and the second conductivity type second region lines up with one end of the gate electrode vertically, and a boundary between the second conductivity type second region and the second conductivity type third region lines up with one end of the photoelectric conversion and accumulation section vertically.

8. A solid-state image capturing element according to claim 5, wherein

the second conductivity type region surrounds a region from the first conductivity type semiconductor region to the second conductivity type second region, the second conductivity type third region, and even the electric charge detecting section.

9. A solid-state image capturing element according to claim 1, wherein

a positive electric potential difference of less than +0.5 V is applied in between the transfer gate electrode and the second conductivity type semiconductor region during a period when the photoelectric conversion and accumulation section photoelectrically converts light into signal charges for electric charge accumulation.

10. A solid-state image capturing element according to claim 9, wherein

the positive electric potential difference is in the range equal to or greater than +0.2 V and less than +0.5 V.

11. An electronic information device including a solid-state image capturing element according to claim 1 as an image input device used in an image capturing section thereof.