Sensing FET integrated with a high-voltage transistor

• US 8,653,583 B2
• Filed: 02/16/2007
• Issued: 02/18/2014
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Banerjee, Sujit, Manley, Martin H.
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US11/707,586
• Publication Number:
  US 20080197406A1
• Time in Patent Office: 2,559 Days
• Field of Search: 257/328, 257/329
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A semiconductor device comprising:

a main vertical high-voltage field-effect transistor (HVFET) structure; and

a sensing FET structure integrated laterally adjacent to the HVFET structure,

the main vertical HVFET structure being formed on a first pillar of semiconductor material, and the sensing FET structure being formed on a second pillar of the semiconductor material, the semiconductor material being formed on a substrate,

the first and second pillars and the substrate being of a first conductivity type,

the first and second pillars each having a top surface and a bottom, the bottom adjoining the substrate, the first and second pillars each extending in a vertical direction from the bottom to the top surface,

the first and second pillars each extending in first and second lateral directions to form a racetrack-shaped layout which includes a pair of substantially parallel, elongated straight sections having a length that extends in the first lateral direction, the pair of straight sections being connected at opposite ends by respective first and second semi-circular sections that span a width of the racetrack-shaped layout in the second lateral direction,

first and second dielectric regions being disposed on opposite sides of each of the first and second pillars,

first and second gate members being respectively disposed adjacent each of the first and second pillars in the first and second dielectric regions at or near the top surface,

the main vertical HVFET structure and the sensing FET structure each having an extended drain region of the first conductivity type, the extended drain of the main vertical HVFET structure being formed in the first pillar above the substrate, and the extended drain of the sensing FET structure being formed in the second pillar above the substrate, the substrate being commonly shared by the main vertical HVFET structure and the sensing FET structure,

the first and second gate members also being commonly shared by the main vertical HVFET structure and the sensing FET structure;

the main vertical HVFET structure further including;

a first body region of a second conductivity type disposed in the first pillar above the extended drain region of the main vertical HVFET structure; and

a first source region disposed at or near the top surface of the first pillar, the first source region being vertically separated from the extended drain region of the main vertical HVFET structure by the first body region;

the sensing FET structure further including;

a second body region of a second conductivity type disposed in the second pillar above the extended drain region of the sensing FET structure; and

a second source region disposed at or near the top surface of the second pillar, the second source region being vertically separated from the extended drain region of the sensing FET structure by the second body region,

wherein the sensing FET structure is operable to sample a small portion of a current that flows in the main vertical HVFET structure, thereby providing an indication of a current flowing through the main vertical HVFET structure.

2. The semiconductor device of claim 1 further comprising first and second field plates respectively disposed in the first and second dielectric regions.

3. The semiconductor device of claim 2 further comprising:

a source electrode that electrically contacts the first source region;

a sensing source electrode that electrically contacts the second source region; and

a drain electrode that electrically contacts a bottom surface of the substrate, the drain electrode being commonly shared by the main vertical HVFET structure and the sensing FET structure.

4. The semiconductor device of claim 3 wherein the source electrode is electrically coupled to the first and second field plates.

5. The semiconductor device of claim 1 further comprising first and second regions of the second conductivity type disposed laterally adjoining the first and second source regions, respectively.

6. The semiconductor device of claim 1 wherein the first pillar comprises a transistor segment of the main vertical HVFET structure, the main vertical HVFET structure comprising a plurality of transistor segments length is at least 30 times greater than the width.

7. An integrated circuit (IC) comprising:

a power field-effect transistor (FET) device structure which comprises a plurality of transistor segments; and

a sensing FET device structure which comprises a single transistor segment, the single transistor segment and each of the plurality of transistor segments each comprising;

a pillar formed on a substrate, the pillar and substrate both being of a first conductivity type, the pillar having a top surface and a bottom, the bottom adjoining the substrate, the pillar extending in a vertical direction from the bottom to the top surface, the pillar extending in first and second lateral directions to form a racetrack-shaped layout which includes a pair of substantially parallel, elongated straight sections having a length that extends in the first lateral direction, the pair of straight sections being connected at opposite ends by respective first and second semi-circular sections that span a width of the racetrack-shaped layout in the second lateral direction;

first and second dielectric regions being disposed on opposite sides of the pillar;

first and second gate members being respectively disposed adjacent the pillar in the first and second dielectric regions, each of the first and second gate members being insulated from the pillar by a thin layer of dielectric material;

wherein the power FET device structure and the sensing FET device structure share a common electrical connection at the bottom of the pillar adjoining the substrate,

the first and second gate members also being commonly shared by the power FET device structure and the sensing FET device structure;

each of the plurality of transistor segments of the power FET device structure further including;

a first extended drain region of the first conductivity type formed in the pillar of the power FET device structure above the substrate,

a first body region of a second conductivity type disposed in the pillar of the power FET device structure above the extended drain region; and

a first source region disposed at or near the top surface of the pillar of the power FET device structure,

the first source region being vertically separated from the extended drain region by the first body region,

the first and second gate members being disposed laterally adjacent the first body region and extending vertically from the first source region to the first extended drain region;

the single transistor segment of the sensing FET device structure further including;

a second extended drain region of the first conductivity type formed in the pillar of the sensing FET device structure above the substrate,

a second body region of a second conductivity type disposed in the pillar of the sensing FET device structure above the extended drain region; and

a second source region disposed at or near the top surface of the pillar of the sensing FET device structure,

the second source region being vertically separated from the extended drain region by the second body region,

the second source region being laterally separated and electrically isolated in the first lateral direction from the first source region,

wherein the sensing FET device structure is operable to sample a small portion of a current that flows in the power FET device structure, thereby providing an indication of a current flowing through the power FET device structure.

8. The IC of claim 7 wherein the single transistor segment and each of the plurality of transistor segments each further comprise:

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates extending vertically from the top surface down to near the substrate,

the first and second field plates being electrically insulated from the first and second gate members.

9. The IC of claim 7 further comprising:

a source electrode that electrically contacts the first source region;

a sensing source electrode that electrically contacts the second source region; and

a drain electrode that electrically contacts a bottom surface of the substrate, the drain electrode being commonly shared by the power FET device structure and the sensing FET device structure.

10. The IC of claim 9 wherein the source electrode is electrically coupled to the first and second field plates of each of the plurality of transistor segments.