Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

• US 8,653,604 B1
• Filed: 09/21/2012
• Issued: 02/18/2014
• Est. Priority Date: 07/26/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Hoffmann, Thomas, Ranade, Pushkar, Shifren, Lucian, Thompson, Scott E.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Patton, Paul
• Application Number:
  US13/624,449
• Time in Patent Office: 515 Days
• Field of Search: 257/E21.633, 257/E21.335, 257/369, 257/192, 257/E21.409, 257/E29.055, 438/199, 438/289, 438/300, 438/514, 438/530
• US Class Current: 257/369
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

Claims

1. An integrated circuit die supporting a plurality of transistor device types formed by a process comprising the steps of:

doping selected portions of a wafer to form a first plurality of wells of a first conductivity type;

doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells, the screen layers being formed using one or more screen layer doses;

growing a substantially undoped epitaxial layer over the screen layer to a defined thickness and uniformity;

forming source and drain structures for the plurality of transistor device types within the undoped epitaxial layer;

doping selected portions of the first plurality of screen layers to introduce diffusion-inhibiting dopant species;

outdiffusing dopants from the screen layer into the epitaxial layer using a thermal cycling process, wherein the threshold voltages of each transistor device type of the plurality of transistor device types are differentiated by distance of dopant migration towards the gate; and

performing halo implants into predetermined portions of the epitaxial layer in alignment with at least one selected source and drain structure, one or more halo implant doses being used to perform the halo implants;

wherein the screen layer has a doping concentration that is greater than a doping concentration of the first plurality of wells;

wherein at least some of the transistor devices of the plurality of transistor device types are formed using a discrete and individualized predetermined combination of the one or more screen layer dose and the one or more halo implant dose.

2. The integrated circuit die of claim 1, further including forming a first plurality of anti-punchthrough regions in said first plurality of wells of a first conductivity type.

3. The integrated circuit die of claim 1, wherein doping selected portions of the first plurality of screen layers comprises implanting one or more elements that act as a dopant migration barrier.

4. The integrated circuit die of claim 1, wherein the diffusion-inhibiting dopant species comprise carbon.

5. The integrated circuit die of claim 1, wherein doping selected portions of the first plurality of wells to form the first plurality of screen layers comprises implanting at least a first dopant species having a first diffusivity in a first portion of the first plurality of screen layers, and implanting a second dopant species having a second diffusivity in a second portion of the first plurality of screen layers, the first diffusivity being greater than the second diffusivity.

6. The integrated circuit die of claim 1, wherein one or more of the transistor device types are formed using a halo implant dose approximately in the range of 5×

10¹² atoms/cm² to 2×

10¹³ atoms/cm².

7. The integrated circuit die of claim 1, wherein one or more of the transistor device types are formed using a halo implant dose approximately in the range of 1×

10¹³ atoms/cm² to 4×

10¹³ atoms/cm².

8. The integrated circuit die of claim 1, wherein the halo implant step is not performed for one or more of the transistor device types.

9. The integrated circuit die of claim 1, the process further comprising the steps of:

forming an anti-punchthrough layer between at least one of the first plurality of wells and at least one of the screen layers that overlies the at least one of the first plurality of wells,

wherein the anti-punchthrough layer has a doping concentration greater than a doping concentration of the at least one well, and less that a doping concentration of the overlying screen layer.

10. The integrated circuit die of claim 2, wherein differentially out-diffusing dopants forms at least a first channel region having a first thickness and a second channel region having a second thickness that is different from the first thickness.

11. The integrated circuit die of claim 10, wherein the first thickness is less than the second thickness, and the screen layer underlying the first channel region has a greater concentration of dopants of relatively high diffusivity than the screen layer underlying the second channel region.

12. The integrated circuit die of claim 1, the process further comprising the step of forming a threshold voltage setting layer above the screen layer and below the surface of the epitaxial layer.

13. The integrated circuit die of claim 1, the process further comprising the step of:

forming shallow trench isolation structures to isolate at least some of the plurality of doped wells from each other,

wherein the shallow trench isolation structures are formed after forming the substantially undoped semiconductive layer.

14. The integrated circuit die of claim 13, wherein the shallow trench isolation structures are formed before performing the halo implants.

15. An integrated circuit die supporting a plurality of transistor device types formed by a process comprising the steps of:

doping selected portions of a wafer to form a first plurality of wells of a first conductivity type;

doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells, the screen layers being formed using one or more screen layer doses;

growing a substantially undoped epitaxial layer over the screen layer to a predetermined thickness and uniformity;

forming source and drain structures for the plurality of transistor device types within the undoped epitaxial layer; and

performing halo implants into predetermined portions of the epitaxial layer in alignment with the source and drain structures of at least one first transistor device type of the plurality of transistor device types, one or more halo implant doses being used to perform the halo implants,

wherein at least one second transistor device type of the plurality of transistor device type is formed without halo implants, and wherein the second transistor device type has less variation of threshold voltage as compared to the first transistor device type.

16. The integrated circuit die of claim 15, wherein the screen layer dose used to form the first transistor device type is different from the screen layer dose used to form the second transistor device type.

17. The integrated circuit die of claim 15, wherein the screen layer dose used to form the first transistor device type is substantially equal to the screen layer dose used to form the second transistor device type.

18. A method of forming a plurality of transistor device types on an integrated circuit, the transistors having a gate disposed over a semiconductive channel, comprising:

doping selected portions of a wafer to form a first plurality of wells of a first conductivity type;

doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells;

doping selected portions of the first plurality of screen layers to introduce diffusion-inhibiting dopant species;

growing a substantially undoped epitaxial layer over the first plurality of screen layers to a defined thickness and uniformity;

out-diffusing dopants from at least one of the first plurality of screen layers into the epitaxial layer to result in discrete threshold voltage devices by way of a thermal cycling process to result in defined degrees of out-diffusion of dopants that are differentiated by distance of dopant migration toward the gate;

wherein doping selected portions of the first plurality of wells to form the first plurality of screen layers comprises implanting at least a first dopant species having a first diffusivity in a first portion of the first plurality of screen layers, and implanting a second dopant species having a second diffusivity in a second portion of the first plurality screen layers, and the first diffusivity is greater than the second diffusivity.

19. The method of claim 18, wherein the screen layer has a doping concentration that is greater than a doping concentration of the first plurality of wells.

20. The method of claim 18, wherein doping selected portions of the first plurality of screen layers comprises implanting one or more elements that act as a dopant migration barrier.

21. The method of claim 20, wherein at least one of the one or more elements that act as a dopant migration barrier comprises carbon.

22. An integrated circuit die supporting a plurality of transistor device types formed by a process comprising the steps of:

doping selected portions of a wafer to form a first plurality of wells of a first conductivity type;

doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells, the screen layers being formed using one or more screen layer doses;

growing a substantially undoped epitaxial layer over the screen layer to a defined thickness and uniformity;

forming source and drain structures for the plurality of transistor device types within the undoped epitaxial layer; and

performing halo implants into predetermined portions of the epitaxial layer in alignment with at least one selected source and drain structure, one or more halo implant doses being used to perform the halo implants;

wherein at least some of the transistor devices of the plurality of transistor device types are formed using a discrete and individualized predetermined combination of the one or more screen layer dose and the one or more halo implant dose;

wherein doping selected portions of the first plurality of wells to form the first plurality of screen layers comprises implanting at least a first dopant species having a first diffusivity in a first portion of the first plurality of screen layers, and implanting a second dopant species having a second diffusivity in a second portion of the first plurality of screen layers, the first diffusivity being greater than the second diffusivity.

23. The integrated circuit die of claim 22, the process further comprising the steps of:

forming an anti-punchthrough layer between at least one of the first plurality of wells and at least one of the screen layers that overlies the at least one of the first plurality of wells,

wherein the anti-punchthrough layer has a doping concentration greater than a doping concentration of the at least one well, and less that a doping concentration of the overlying screen layer.

24. The integrated circuit die of claim 22, the process further comprising the step of forming a threshold voltage setting layer above the screen layer and below the surface of the epitaxial layer.