Semiconductor device packages with electromagnetic interference shielding

• US 8,653,633 B2
• Filed: 07/05/2011
• Issued: 02/18/2014
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Chiu, Chi-Tsung, Hung, Chih-Pin
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US13/176,679
• Publication Number:
  US 20110260301A1
• Time in Patent Office: 959 Days
• Field of Search: 257/659, 257/660, 257/708, 257/E23.114, 361/800, 361/816, 361/818
• US Class Current: 257/659
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49153 : with shaping or forcing terminal into base aperture
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49789 : Obtaining plural product pieces from unitary workpiece

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a substrate including

an upper surface,

a lower surface,

a lateral surface disposed adjacent a periphery of the substrate and extending between the upper surface and the lower surface of the substrate, and

a grounding element being a via disposed adjacent the periphery of the substrate, the grounding element being electrically connected to a grounding electrical interconnect in the substrate, being electrically exposed adjacent the lateral surface of the substrate, and partially extending between the upper surface and the lower surface of the substrate, such that a height of the grounding element is less than a thickness of the substrate;

a package body disposed adjacent the upper surface of the substrate, the package body including exterior surfaces that include a lateral surface, the lateral surface of the package body being substantially coplanar with the lateral surface of the substrate; and

an electromagnetic interference shield disposed adjacent the exterior surfaces of the package body and electrically connected to the grounding element.

2. The semiconductor device package of claim 1, wherein the substrate includes a pair of internal grounding layers, and the grounding element extends between the pair of internal grounding layers.

3. The semiconductor device package of claim 1, wherein the grounding element comprises a partial via.

4. The semiconductor device package of claim 3, wherein the partial via is semi-cylindrical.

5. The semiconductor device package of claim 1, wherein the grounding element further comprises a partial upper via pad and a partial lower via pad.

6. The semiconductor device package of claim 5, further comprising a partial via disposed between the upper and lower via pads.

7. The semiconductor device package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along the lateral surface of the substrate.

8. The semiconductor device package of claim 7, wherein a lower end of the lateral portion is substantially aligned with the lower surface of the substrate.

9. A semiconductor device package, comprising:

a substrate including

a first surface,

a second opposite surface,

an electrically conductive layer disposed between the first surface and the second surface of the substrate, and

a grounding element extending between the electrically conductive layer and one of the first and second surfaces of the substrate, the grounding element including a first end, a second end, and a lateral surface, the first end being disposed between the first and second surfaces of the substrate and being spaced apart therefrom, the second end being disposed adjacent one of the first and second surfaces of the substrate, the lateral surface being disposed adjacent a periphery of the substrate;

a package body disposed adjacent the substrate, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element.

10. The semiconductor device package of claim 9, wherein the substrate further includes a lateral surface extending between the first and second surfaces of the substrate, the lateral surface of the substrate being substantially planar and substantially orthogonal to the second surface of the substrate, and the lateral surface of the grounding element is electrically exposed adjacent the lateral surface of the substrate.

11. The semiconductor device package of claim 9, wherein the grounding element comprises a partial via.

12. The semiconductor device package of claim 11, wherein the partial via is semi-cylindrical.

13. The semiconductor device package of claim 9, wherein the grounding element further comprises a partial upper via pad and a partial lower via pad.

14. The semiconductor device package of claim 13, further comprising a partial via disposed between the partial upper and lower via pads.

15. The semiconductor device package of claim 9, wherein the electromagnetic interference shield is a conformal shield that includes a first layer and a second layer disposed adjacent the first layer, and the first layer and the second layer comprise different electrically conductive materials.

16. A semiconductor device package, comprising:

a substrate including

an upper surface,

a lower surface,

a pair of electrically conductive layers disposed between the upper surface and the lower surface of the substrate, and

a grounding element extending between the electrically conductive layers, the grounding element including an upper end, a lower end, and a lateral surface, the upper end being disposed between the upper and lower surfaces of the substrate and being spaced apart therefrom, the lower end being disposed between the upper and lower surfaces of the substrate and being spaced apart therefrom, the lateral surface being disposed adjacent a periphery of the substrate;

a package body disposed adjacent the substrate, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element.

17. The semiconductor device package of claim 16, wherein the lateral surface is a partial via.

18. The semiconductor device package of claim 17, wherein the partial via is semi-cylindrical.

19. The semiconductor device package of claim 16, wherein the upper end is a partial via pad.

20. The semiconductor device package of claim 19, wherein the lower end is a partial via pad.