EMI-shielded semiconductor devices and methods of making

• US 8,653,634 B2
• Filed: 06/11/2012
• Issued: 02/18/2014
• Est. Priority Date: 06/11/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chiu, Chi Tsung, Ou, Ying-Te
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US13/493,576
• Publication Number:
  US 20130328176A1
• Time in Patent Office: 617 Days
• Field of Search: 257/659, 257/415, 257/E29.324, 438/51
• US Class Current: 257/659
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield.

Claims

1. A semiconductor package, comprising:

a semiconductor die;

a micro-structure element disposed on an upper surface of the semiconductor die;

a conductive element disposed on the upper surface of the semiconductor die, the conductive element circumscribing the micro-structure element and forming a cavity where the micro-structure element resides; and

a shield disposed over the conductive element, the cavity, and the micro-structure element to provide electromagnetic interference (EMI) shielding for the micro-structure element;

wherein the semiconductor die includes at least one through hole, and the shield is electrically connected the conductive element and the at least one through hole.

2. The semiconductor package of claim 1, wherein the conductive element extends to a periphery of the semiconductor die.

3. The semiconductor package of claim 1, wherein the conductive element is set back from a periphery of the semiconductor die.

4. The semiconductor package of claim 1, wherein the shield includes a base layer and a metal shielding layer covering the base layer.

5. The semiconductor package of claim 1, wherein the shield comprises only a single metal layer.

6. The semiconductor package of claim 1, wherein the shield includes a first thickness in an area located over the micro-structure element, and a second thickness in areas not located over the micro-structure element, and the first thickness is less than the second thickness.

7. The semiconductor package of claim 6, wherein the micro-structure element includes a first element and a second element, and the shield comprises the first thickness in areas located over the first and second micro-structure elements, and the second thickness in areas not located over the first and second micro-structure elements.

8. The semiconductor package of claim 1, wherein the semiconductor die is devoid of active circuitry.

9. A semiconductor package, comprising:

a semiconductor die;

a micro-structure element disposed on an upper surface of the semiconductor die;

a conductive element disposed on the upper surface of the semiconductor die and circumscribing the micro-structure element; and

a shield disposed over the micro-structure element to provide electromagnetic interference (EMI) shielding for the micro-structure element;

wherein the shield comprises a first thickness in an area located over the micro-structure element, and a second thickness in areas not located over the micro-structure element, and the first thickness is less than the second thickness; and

wherein the semiconductor die includes at least one through hole, and the shield is electrically connected to the conductive element and the at least one through hole.

10. The semiconductor package of claim 9, wherein the shield includes an opening that exposes a space beneath the shield surrounding the micro-structure element to the ambient.

11. The semiconductor package of claim 9, wherein the conductive element extends to a periphery of the semiconductor die.

12. The semiconductor package of claim 9, wherein the conductive element is set back from a periphery of the semiconductor die.

13. The semiconductor package of claim 9, wherein the shield includes a base layer and a metal layer covering the base layer.

14. The semiconductor package of claim 9, wherein the shield comprises only a single metal layer.

15. The semiconductor package of claim 9, wherein the micro-structure element includes a first element and a second element, and the shield comprises a first thickness in areas located over the first and second micro-structure elements, and a second thickness in areas not located over the first and second micro-structure elements, and the first thickness is less than the second thickness.

16. The semiconductor package of claim 9, wherein the semiconductor die is devoid of active circuitry.