Differential interfaces for power domain crossings

• US 8,653,853 B1
• Filed: 12/31/2006
• Issued: 02/18/2014
• Est. Priority Date: 12/31/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shumarayev, Sergey, Hoang, Tim Tri, Smith, Lawrence David
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): Lo, Christopher
• Application Number:
  US11/618,828
• Time in Patent Office: 2,606 Days
• Field of Search: 326/26, 326/30, 326 81- 83, 326 86- 87, 326/112, 326/115, 327108-109, 327/333
• US Class Current: 326/82
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/0175 Coupling arrangements; Interface arrangements interface arrangements for digital computers G06F3/00, G06F13/00
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17784 for supply voltage
• CPC Class Codes: H03K 19/17788 for input/output [I/O] voltages

Abstract

Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

Claims

1. An integrated circuit comprising a differential interface, wherein the differential interface comprises:

a driver circuit comprising an input to receive a single-ended input signal and outputs to output differential output signals, the driver circuit to receive a first power supply voltage and a first ground voltage in a first power supply domain in the integrated circuit, wherein the driver circuit further comprises a first current mode logic circuit, wherein the first current mode logic circuit comprises first and second transistors, wherein a drain of the first transistor is coupled to a first resistor, wherein a drain of the second transistor is coupled to a second resistor, wherein the first resistor is coupled to the second resistor, and wherein a source of the first transistor is coupled to a source of the second transistor and to a current source; and

a receiver circuit comprising inputs to receive the differential output signals of the driver circuit and an output to output a single-ended output signal, the receiver circuit to receive a second power supply voltage and a second ground voltage in a second power supply domain in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, and wherein the driver circuit and the receiver circuit are in the integrated circuit,

wherein the receiver circuit further comprises a second current mode logic circuit having differential inputs coupled to differential outputs of the first current mode logic circuit, wherein the second current mode logic circuit comprises third and fourth transistors, wherein a drain of the third transistor is coupled to a third resistor, wherein a drain of the fourth transistor is coupled to a fourth resistor, wherein the third and the fourth resistors are coupled to a node at the second power supply voltage, and wherein a source of the third transistor is coupled to a source of the fourth transistor.

2. The integrated circuit defined in claim 1 wherein the driver circuit further comprises a splitter circuit coupled to the input of the driver circuit and to the first current mode logic circuit.

7. The integrated circuit defined in claim 1 wherein the receiver circuit further comprises an amplifier coupled to differential outputs of the second current mode logic circuit.

8. The integrated circuit defined in claim 7 wherein the receiver circuit further comprises an inverter coupled to a single-ended output of the amplifier.

9. The integrated circuit defined in claim 1 wherein the integrated circuit is a programmable integrated circuit, and the single-ended output signal of the receiver circuit is transmitted to a configuration scan register.

3. An integrated circuit comprising a differential interface, wherein the differential interface comprises:

a driver circuit comprising an input to receive a single-ended input signal and outputs to output differential output signals, the driver circuit to receive a first power supply voltage and a first ground voltage in a first power supply domain in the integrated circuit; and

a receiver circuit comprising inputs to receive the differential output signals of the driver circuit and an output to output a single-ended output signal, the receiver circuit to receive a second power supply voltage and a second ground voltage in a second power supply domain in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, wherein the driver circuit and the receiver circuit are in the integrated circuit,

wherein the receiver circuit comprises a current mode logic circuit comprising first and second transistors, wherein the first and the second transistors receive the differential output signals of the driver circuit, wherein a drain of the first transistor is coupled to a first resistor, wherein a drain of the second transistor is coupled to a second resistor, wherein the first and the second resistors are coupled to a node at the second power supply voltage, wherein the second power supply voltage is above the second ground voltage, and wherein a source of the first transistor is coupled to a source of the second transistor and to a current source.

4. The integrated circuit defined in claim 3 wherein the receiver circuit further comprises an amplifier circuit coupled to the current mode logic circuit.

5. The integrated circuit defined in claim 4 wherein the amplifier circuit comprises a third transistor coupled to the drain of the first transistor and a fourth transistor coupled to the drain of the second transistor.

6. An integrated circuit comprising a differential interface, wherein the differential interface comprises:

a driver circuit comprising an input to receive a single-ended input signal and outputs to output differential output signals, the driver circuit to receive a first power supply voltage and a first ground voltage in a first power supply domain in the integrated circuit; and

a receiver circuit comprising inputs to receive the differential output signals of the driver circuit and an output to output a single-ended output signal, the receiver circuit to receive a second power supply voltage and a second ground voltage in a second power supply domain in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, wherein the driver circuit and the receiver circuit are in the integrated circuit,

wherein the receiver circuit further comprises a current mode logic circuit comprising first and second transistors, wherein the first and the second transistors receive the differential output signals of the driver circuit, wherein a drain of the first transistor is coupled to a first resistor, wherein a drain of the second transistor is coupled to a second resistor, wherein the first and the second resistors are coupled together, wherein a source of the first transistor is coupled to a source of the second transistor and to a current source, and

wherein the receiver circuit further comprises an amplifier comprising a third transistor coupled to the drain of the first transistor, and a fourth transistor coupled to the drain of the second transistor.

10. A method comprising:

driving a signal from a single-ended input to differential outputs of a driver circuit, wherein the driver circuit receives a first power supply voltage and a first ground voltage in a first power supply domain, wherein the first power supply domain is in an integrated circuit, wherein driving a signal from the single-ended input to the differential outputs of the driver circuit further comprises driving the signal through a first current mode logic circuit in the driver circuit, wherein the first current mode logic circuit comprises first and second transistors and a first resistor coupled between a drain of the first transistor and a second resistor, wherein the second resistor is coupled to a drain of the second transistor; and

driving signals from differential inputs to a single-ended output of a receiver circuit, wherein the receiver circuit receives the signals from the differential outputs of the driver circuit, wherein the receiver circuit receives a second power supply voltage and a second ground voltage in a second power supply domain, wherein the second power supply domain is in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, and wherein the driver circuit and the receiver circuit are in the integrated circuit,

wherein driving signals from differential inputs to a single-ended output of a receiver circuit further comprises driving the signals from the differential inputs to the single-ended output of the receiver circuit with a second current mode logic circuit comprising third and fourth transistors that are coupled to the differential outputs of the driver circuit, wherein a drain of the third transistor is coupled to a third resistor, wherein a drain of the fourth transistor is coupled to a fourth resistor, wherein the third and the fourth resistors are coupled to a node at the second power supply voltage, and wherein a source of the third transistor is coupled to a source of the fourth transistor.

11. The method defined in claim 10 wherein driving a signal from the single-ended input to the differential outputs of the driver circuit further comprises driving the signal from the single-ended input through a splitter circuit in the driver circuit.

13. The method defined in claim 10 wherein the second current mode logic circuit has differential inputs coupled to differential outputs of the first current mode logic circuit.

14. The method defined in claim 10 wherein a gate of the third transistor is coupled to the drain of the first transistor, and wherein a gate of the fourth transistor is coupled to the drain of the second transistor.

15. The method defined in claim 10 wherein the first current mode logic circuit further comprises a current source coupled to a source of the first transistor and to a source of the second transistor.

16. The method defined in claim 10 further comprising:

transmitting a signal from the single-ended output of the receiver circuit through a plurality of configuration scan registers in the second power supply domain.

12. A method comprising:

driving a signal from a single-ended input to differential outputs of a driver circuit, wherein the driver circuit receives a first power supply voltage and a first ground voltage in a first power supply domain, wherein the first power supply domain is in an integrated circuit; and

driving signals from differential inputs to a single-ended output of a receiver circuit, wherein the receiver circuit receives the signals from the differential outputs of the driver circuit, wherein the receiver circuit receives a second power supply voltage and a second ground voltage in a second power supply domain, wherein the second power supply domain is in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, and wherein the driver circuit and the receiver circuit are in the integrated circuit,

wherein driving signals from differential inputs to a single-ended output of a receiver circuit further comprises driving the signals from the differential inputs to the single-ended output of the receiver circuit with a current mode logic circuit comprising first and second transistors that are coupled to the differential outputs of the driver circuit, wherein a drain of the first transistor is connected directly to a first resistor, wherein a drain of the second transistor is connected directly to a second resistor, wherein the first resistor is coupled to the second resistor, and wherein a source of the first transistor is connected directly to a source of the second transistor and to a current source.

17. An integrated circuit comprising a differential interface, wherein the differential interface comprises:

first means for converting a single-ended input signal into differential output signals, the first means for converting to receive a first power supply voltage and a first ground voltage in a first power supply domain in the integrated circuit; and

second means for converting the differential output signals into a single-ended output signal, the second means for converting to receive a second power supply voltage and a second ground voltage in a second power supply domain in the integrated circuit, wherein the first and the second power supply domains are electrically isolated from each other in the integrated circuit, wherein the first means and the second means for converting are in the integrated circuit,

wherein the second means for converting comprises a first current mode logic circuit that comprises a first transistor, a second transistor coupled to the first transistor, a first resistor coupled between a drain of the first transistor and a node at the second power supply voltage, wherein the second power supply voltage is above the second ground voltage, and a second resistor coupled between a drain of the second transistor and the node at the second power supply voltage.

18. The integrated circuit defined in claim 17 wherein the first means for converting comprises a splitter circuit.

19. The integrated circuit defined in claim 18 wherein the first means for converting further comprises a second current mode logic circuit coupled to the splitter circuit, wherein the second current mode logic circuit comprises third and fourth transistors and a current source, wherein the current source is coupled to a source of the third transistor and to a source of the fourth transistor.