Semiconductor device and manufacturing method thereof

• US 8,654,231 B2
• Filed: 03/01/2011
• Issued: 02/18/2014
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Ikeda, Takayuki, Tamura, Hikaru, Kozuma, Munehiro, Ikeda, Masataka, Aoki, Takeshi
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US13/037,889
• Publication Number:
  US 20110215323A1
• Time in Patent Office: 1,085 Days
• Field of Search: 348/294, 348/308, 348/296, 250/208.1, 257290-294
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 31/1055 the devices comprising amorphous materials of Group IV of the Periodic Table
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Claims

1. A semiconductor device comprising:

a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising;

a photodiode;

a signal charge accumulation portion;

a charge accumulation control transistor, wherein one of a source and a drain of the charge accumulation control transistor is electrically connected to the photodiode and the other of the source and the drain of the charge accumulation control transistor is electrically connected to the signal charge accumulation portion;

a reset transistor, wherein one of a source and a drain of the reset transistor is electrically connected to the signal charge accumulation portion; and

an amplifying transistor, wherein a gate of the amplifying transistor is electrically connected to the signal charge accumulation portion,

wherein a channel formation region in at least one of the charge accumulation control transistor and the reset transistor comprises an oxide semiconductor,

wherein after a reset operation of the signal charge accumulation portion is performed in the plurality of pixels at substantially the same time, a charge accumulation operation by the photodiode is performed in the plurality of pixels at substantially the same time, and a read operation of a signal from each of the plurality of pixels is performed per row, and

wherein gates of the reset transistors in the plurality of pixels are electrically connected to each other.

2. The semiconductor device according to claim 1,

wherein each of the plurality of pixels further comprises a selection transistor, and

wherein one of a source and a drain of the selection transistor is electrically connected to the one of the source and the drain of the amplifying transistor.

3. The semiconductor device according to claim 1, wherein gates of the charge accumulation control transistors in the plurality of pixels are electrically connected to each other.

4. The semiconductor device according to claim 1, wherein the other of the source and the drain of the reset transistor is electrically connected to one of a source and a drain of the amplifying transistor.

5. An electronic device comprising the semiconductor device according to claim 1.

6. A semiconductor device comprising:

a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising;

a photodiode;

a charge accumulation control transistor, wherein one of a source and a drain of the charge accumulation control transistor is electrically connected to the photodiode;

a reset transistor, wherein one of a source and a drain of the reset transistor is electrically connected to the other of the source and the drain of the charge accumulation control transistor; and

an amplifying transistor, wherein a gate of the amplifying transistor is electrically connected to the other of the source and the drain of the charge accumulation control transistor and the one of the source and the drain of the reset transistor,

wherein a channel formation region in at least one of the charge accumulation control transistor and the reset transistor comprises an oxide semiconductor,

wherein gates of the reset transistors in the plurality of pixels arranged in the matrix are electrically connected to each other, and

wherein gates of the charge accumulation control transistors in the plurality of pixels are electrically connected to each other.

7. The semiconductor device according to claim 6,

wherein each of the plurality of pixels further comprises a selection transistor, and

wherein one of a source and a drain of the selection transistor is electrically connected to the one of the source and the drain of the amplifying transistor.

8. The semiconductor device according to claim 6, wherein the other of the source and the drain of the reset transistor is electrically connected to one of a source and a drain of the amplifying transistor.

9. An electronic device comprising the semiconductor device according to claim 6.

10. A semiconductor device comprising:

a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising;

a photodiode;

a signal charge accumulation portion electrically connected to the photodiode;

a transistor, wherein a gate of the transistor is electrically connected to the signal charge accumulation portion, and

a capacitor, wherein one of electrodes of the capacitor is electrically connected to the signal charge accumulation portion,

wherein a channel formation region in the transistor comprises an oxide semiconductor, and

wherein after a reset operation of the signal charge accumulation portion is performed in the plurality of pixels arranged in the matrix at substantially the same time, a charge accumulation operation by the photodiode is performed in the plurality of pixels at substantially the same time, and a read operation of a signal from each of the plurality of pixels is performed per row.

11. The semiconductor device according to claim 10, wherein the transistor is an amplifying transistor.

12. An electronic device comprising the semiconductor device according to claim 10.

13. A driving method of a semiconductor device comprising a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising a photodiode, a signal charge accumulation portion, a charge accumulation control transistor, a reset transistor, an amplifying transistor, and a selection transistor, wherein one of a source and a drain of the charge accumulation control transistor is electrically connected to the photodiode, the other of the source and the drain of the charge accumulation control transistor is electrically connected to the signal charge accumulation portion, one of a source and a drain of the reset transistor is electrically connected to the signal charge accumulation portion, a gate of the amplifying transistor is electrically connected to the signal charge accumulation portion, and one of a source and a drain of the selection transistor is electrically connected to one of a source and a drain of the amplifying transistor, comprising the steps of:

turning on the charge accumulation control transistors in the plurality of pixels simultaneously;

turning on the reset transistors in the plurality of pixels simultaneously, and setting a potential of the signal charge accumulation portion in each of the plurality of pixels to a reset potential;

turning off the reset transistors in the plurality of pixels simultaneously, and changing the potential of the signal charge accumulation portion in each of the plurality of pixels;

turning off the charge accumulation control transistors in the plurality of pixels simultaneously, and holding the potential of the signal charge accumulation portion in each of the plurality of pixels; and

turning on the selection transistors per row sequentially, and outputting a signal corresponding to the potential of the signal charge accumulation portion in each of the plurality of pixels from the amplifying transistor in each of the plurality of pixels,

wherein a channel formation region of at least one of the charge accumulation control transistor and the reset transistor comprises an oxide semiconductor.

14. The driving method of a semiconductor device according to claim 13, wherein the reset transistors of the plurality of pixels are operated with a signal.

15. The driving method of a semiconductor device according to claim 13, wherein the charge accumulation control transistors of the plurality of pixels are operated with a signal.

16. A driving method of a semiconductor device comprising a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising a photodiode, a signal charge accumulation portion, a charge accumulation control transistor, a reset transistor, an amplifying transistor, and a selection transistor, wherein one of a source and a drain of the charge accumulation control transistor is electrically connected to the photodiode, the other of the source and the drain of the charge accumulation control transistor is electrically connected to the signal charge accumulation portion, one of a source and a drain of the reset transistor is electrically connected to the signal charge accumulation portion, a gate of the amplifying transistor is electrically connected to the signal charge accumulation portion, and one of a source and a drain of the selection transistor is electrically connected to one of a source and a drain of the amplifying transistor, comprising the steps of:

turning on the charge accumulation control transistor in each of the plurality of the pixels simultaneously;

turning on the reset transistor in each of the plurality of the pixels simultaneously, and setting a potential of the signal charge accumulation portion in each of the plurality of the pixels to a reset potential;

turning off the charge accumulation control transistor in each of the plurality of the pixels simultaneously, and changing a potential of a cathode of the photodiode in each of the plurality of the pixels;

turning off the reset transistor in each of the plurality of the pixels simultaneously, and holding the potential of the signal charge accumulation portion in each of the plurality of the pixels;

turning on the charge accumulation control transistor in each of the plurality of the pixels simultaneously, and changing the potential of the signal charge accumulation portion in each of the plurality of the pixels;

turning off the charge accumulation control transistor in each of the plurality of the pixels simultaneously, and holding the potential of the signal charge accumulation portion; and

turning on the selection transistors per row sequentially, and outputting a signal corresponding to the potential of the signal charge accumulation portion in each of the plurality of the pixels from the amplifying transistor in each of the plurality of the pixels,

wherein a channel formation region in at least one of the charge accumulation control transistor and the reset transistor comprises an oxide semiconductor.

17. The driving method of a semiconductor device according to claim 16, wherein the reset transistors of the plurality of pixels are operated with a signal.

18. The driving method of a semiconductor device according to claim 16, wherein the charge accumulation control transistors of the plurality of pixels are operated with a signal.