Semiconductor device and driving method thereof

• US 8,654,566 B2
• Filed: 08/31/2011
• Issued: 02/18/2014
• Est. Priority Date: 09/03/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagatsuka, Shuhei, Matsuzaki, Takanori, Inoue, Hiroki, Kato, Kiyoshi
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/221,947
• Publication Number:
  US 20120056647A1
• Time in Patent Office: 902 Days
• Field of Search: 365/149, 365/183, 365/184, 365/185.02, 365/185.09, 365/185.17, 365/210.11, 365/51, 365/63, 365/72
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.

Claims

1. A driving method for a semiconductor device, the semiconductor device comprises a memory cell including:

a first transistor comprising a first gate electrode; and

a second transistor comprising;

a second channel formation region that overlaps with at least a part of one of a source and a drain of the first transistor with an insulating layer interposed therebetween; and

a second gate electrode over the second channel fat nation region,

wherein one of a source and a drain of the second transistor is electrically connected to the first gate electrode so that a node is formed,

the driving method comprising the steps of;

turning on the second transistor so that charge is supplied to the node,

turning off the second transistor so that charge is held in the node, and

supplying a second potential to the second gate electrode at least when a first potential is supplied to the one of the source and the drain of the first transistor in a period during which charge needs to be held in the node,

wherein the second potential has opposite polarity with the first potential.

2. The driving method for the semiconductor device according to claim 1,

wherein the second transistor further comprising a second gate insulating layer between the second gate electrode and the second channel formation region,

wherein the second potential satisfies a following formula (1):

3. The driving method for the semiconductor device according to claim 1,

wherein the second transistor further comprising a second gate insulating layer between the second gate electrode and the second channel formation region, and

wherein the semiconductor device further comprising a capacitor that comprises one of a source and a drain electrode of the second transistor, the second gate insulating layer, and a conductive layer.

4. The driving method for the semiconductor device according to claim 3, wherein the one of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor.

5. The semiconductor device according to claim 1, wherein a channel formation region of the first transistor and the second channel formation region includes different semiconductor material.

6. The semiconductor device according to claim 1, wherein the second channel formation region includes an oxide semiconductor.

7. A driving method for a semiconductor device, the semiconductor device comprises a memory cell including:

a first transistor comprising a first gate electrode;

a second transistor comprising;

a second gate electrode that overlaps with at least a part of one of a source and a drain of the first transistor with a first insulating layer interposed therebetween; and

a second channel formation region over the second gate electrode; and

a wiring over the second transistor with a second insulating layer interposed therebetween,

wherein one of a source and a drain of the second transistor is electrically connected to the first gate electrode so that a node is formed,

the driving method comprising the steps of;

turning on the second transistor so that charge is supplied to the node,

turning off the second transistor so that charge is held in the node, and

supplying a second potential to the second gate electrode at least when a first potential is supplied to the wiring in a period during which charge needs to be held in the node,

wherein the second potential has opposite polarity with the first potential.

8. The driving method for the semiconductor device according to claim 7,

wherein the second transistor further comprising a second gate insulating layer between the second gate electrode and the second channel formation region,

wherein the second potential satisfies a following formula (2):

9. The driving method for the semiconductor device according to claim 7,

wherein the second transistor further comprising a second gate insulating layer between the second gate electrode and the second channel formation region, and

wherein the semiconductor device further comprising a capacitor that comprises one of a source and a drain electrode of the first transistor, the second gate insulating layer, and a conductive layer.

10. The driving method for the semiconductor device according to claim 9, wherein the one of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor.

11. The driving method for the semiconductor device according to claim 7, wherein a channel formation region of the first transistor and the second channel formation region includes different semiconductor material.

12. The driving method for the semiconductor device according to claim 7, wherein the second channel formation region includes an oxide semiconductor.

13. A driving method for a semiconductor device, the semiconductor device comprising:

a plurality of bit lines;

a plurality of source lines;

a plurality of write word lines;

a plurality of write-read word lines; and

a memory cell array comprising a plurality of memory cells, one of the plurality of the memory cells comprising;

a first transistor including a first gate electrode, a first source region, a first drain region, and a first channel formation region;

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region provided so as to overlap at least part of one of the first source region and the first drain region; and

a capacitor,

wherein one of the plurality of source lines is electrically connected to the first source region,

wherein one of the plurality of bit lines is electrically connected to the first drain region and the second source electrode,

wherein one of the plurality of write-read word lines is electrically connected to one electrode of the capacitor,

wherein one of the write word lines is electrically connected to the second gate electrode,

wherein the first gate electrode, the second drain electrode, and the other electrode of the capacitor are electrically connected to one another to form a node where charge is held,

the driving method comprising the steps of;

supplying a first potential to one of the plurality of write word line and a second potential to the other of the plurality of write word lines in unselected rows at least when a third potential is supplied to the plurality of bit lines in a writing period of the one of the memory cells, and

supplying a fourth potential to the plurality of write word lines at least when a fifth potential is supplied to the plurality of bit lines in a reading period of the one of the memory cells,

wherein the first potential, the third potential and the fifth potential have a same polarity, and

wherein the second potential and the fourth potential have a same polarity that is opposite polarity with the first potential.

14. The driving method for the semiconductor device according to claim 13, wherein a channel formation region of the first transistor and the second channel formation region includes different semiconductor material.

15. The driving method for the semiconductor device according to claim 13, wherein the second channel formation region includes an oxide semiconductor.