High bandwidth memory interface

• US 8,654,573 B2
• Filed: 01/17/2013
• Issued: 02/18/2014
• Est. Priority Date: 07/27/1998
• Status: Expired due to Fees

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Gillingham, Peter B., Millar, Bruce
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US13/743,794
• Publication Number:
  US 20130132761A1
• Time in Patent Office: 397 Days
• Field of Search: 365/154, 365/189.011, 365/189.02, 365/189.15, 365/189.16, 365/189.05, 365/189.12, 365/233.1, 365/233.11
• US Class Current: 365/154
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

Claims

1. A semiconductor device comprising:

a first flip-flop configured to be driven by an even internal clock to sample even output data of the semiconductor device;

a second flip-flop configured to be driven by an odd internal clock to sample odd output data of the semiconductor device;

a third flip-flop configured to be driven by the even internal clock to sample the odd internal clock; and

a fourth flip-flop configured to be driven by the odd internal clock to sample the even internal clock.

2. The semiconductor device of claim 1 further comprising an input to receive a clock signal.

3. The semiconductor device of claim 2 further comprising first and second independently adjustable delays, the first independently adjustable delay configured to receive the clock signal and generate the even internal clock, and the second independently adjustable delay configured to receive the clock signal and generate the odd internal clock.

4. The semiconductor device of claim 1 wherein each of the flip-flops is a D flip-flop.

5. A method carried out in a semiconductor device, the method comprising:

sampling even output data of the semiconductor device by driving a first flip-flop with an even internal clock;

sampling odd output data of the semiconductor device by driving a second flip-flop with an odd internal clock;

sampling the odd internal clock by driving a third flip-flop with the even internal clock; and

sampling the even internal clock by driving a fourth flip-flop with the odd internal clock.

6. The method of claim 5 further comprising receiving a clock signal at an input of the semiconductor device.

7. The method of claim 6 further comprising:

generating the even internal clock using a first independently adjustable delay that receives the clock signal; and

generating the odd internal clock using a second independently adjustable delay that receives the clock signal.

8. The method of claim 5 wherein each of the flip-flops is a D flip-flop.