Robust SRAM memory cell capacitor plate voltage generator

• US 8,654,574 B2
• Filed: 03/08/2013
• Issued: 02/18/2014
• Est. Priority Date: 12/31/2008
• Status: Expired due to Fees

• Current Assignee: Medtronic Incorporated (Medtronic Plc), STMicroelectronics Incorporated (STMicroelectronics NV), STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: Medtronic Incorporated (Medtronic Plc), STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Walsh, Kevin K., Gerrish, Paul F., Tyler, Larry E., Lysinger, Mark A., McClure, David C., Jacquet, Franois
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US13/791,827
• Publication Number:
  US 20130182523A1
• Time in Patent Office: 347 Days
• Field of Search: 365/154, 365/149, 365/189.09
• US Class Current: 365/154
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Claims

1. An implantable cardiac defibrillator comprising:

a battery;

a memory coupled to the battery, the memory having;

a plurality of memory cells, each memory cell respectively including;

a first capacitor; and

a second capacitor in series with the first capacitor, the first and second capacitors being coupled together at a common node; and

a voltage generator including a transistor connected to be always in an off condition and configured to generate a capacitor supply voltage by a leakage current of the transistor in said off condition, the voltage generator configured to supply the leakage current to the respective common nodes of the memory cells; and

defibrillation electrodes coupled to the battery.

2. The implantable cardiac defibrillator of claim 1, wherein each memory cell is an SRAM memory cell having a first inverter, the first and second capacitors being coupled in series between an input and an output of the first inverter.

3. The implantable cardiac defibrillator of claim 1, wherein the capacitor supply voltage is approximately midway between a voltage of a first supply rail and a voltage of a second supply rail.

4. The implantable cardiac defibrillator of claim 3, wherein the first transistor is coupled between a first voltage supply node and a second voltage supply node.

5. The implantable cardiac defibrillator of claim 4, wherein a voltage difference between the first voltage supply node and second voltage supply node is smaller than a voltage difference between the first supply rail and the second supply rail.

6. The implantable cardiac defibrillator of claim 1, wherein the leakage current compensates for a leakage of at least one of the first or second capacitors.

7. The implantable cardiac defibrillator of claim 1, wherein the voltage generator further includes an additional transistor coupled in series with said transistor, wherein said additional transistor is also connected to be always in an off condition and configured to assist in the generation of the capacitor supply voltage by an additional leakage current of the additional transistor in said off condition.

8. The implantable cardiac defibrillator of claim 7, wherein a series connection node between the series coupled transistor and additional transistor is directly connected to said common node.

9. The implantable cardiac defibrillator of claim 1, wherein the transistor is a p-channel transistor having its gate terminal directly connected to its source terminal.

10. The implantable cardiac defibrillator of claim 1, wherein the transistor is an n-channel transistor having its gate terminal directly connected to a voltage node at a voltage equal to or lower than a voltage at its source node.

11. The implantable cardiac defibrillator of claim 1, wherein the transistor is a p-channel transistor having its gate terminal directly connected to a voltage node at a voltage equal to or exceeding a voltage at its source node.

12. An internal pacemaker comprising:

a battery;

a memory coupled to the battery, the memory having;

a plurality of memory cells, each memory cell respectively including;

a first capacitor; and

a second capacitor in series with the first capacitor, the first and second capacitors being coupled together at a common node; and

a voltage generator including a transistor connected to be always in an off condition and configured to generate a capacitor supply voltage by a leakage current of the transistor in said off condition, the voltage generator configured to supply the leakage current to the respective common nodes of the memory cells; and

electrodes coupled to the battery.

13. The internal pacemaker of claim 12, wherein the leakage current compensates for a leakage of at least one of the first or second capacitors.

14. The internal pacemaker of claim 12, wherein the voltage generator further includes an additional transistor coupled in series with said transistor, wherein said additional transistor is also connected to be always in an off condition and configured to assist in the generation of the capacitor supply voltage by an additional leakage current of the additional transistor in said off condition.

15. The internal pacemaker of claim 14, wherein a series connection node between the series coupled transistor and additional transistor is directly connected to said common node.

16. The internal pacemaker of claim 12 wherein the transistor is a p-channel transistor having its gate terminal directly connected to its source terminal.

17. The internal pacemaker of claim 12 wherein the transistor is an n-channel transistor having its gate terminal directly connected to a voltage node at a voltage equal to or lower than a voltage at its source node.

18. The internal pacemaker of claim 12 wherein the transistor is a p-channel transistor having its gate terminal directly connected to a voltage node at a voltage equal to or exceeding a voltage at its source node.