Non-volatile semiconductor memory device equipped with an oxide semiconductor writing transistor having a small off-state current
First Claim
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1. A semiconductor device comprising:
- a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring;
a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor;
a first driver circuit electrically connected to the first wiring;
a second driver circuit electrically connected to the second wiring and the third wiring;
a third driver circuit electrically connected to the fourth wiring; and
a fourth driver circuit electrically connected to the fifth wiring,wherein;
the second transistor comprises an oxide semiconductor layer comprising a channel formation region,the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,the second wiring is electrically connected to one of the first source electrode and the first drain electrode,the first wiring is electrically connected to the other of the first source electrode and the second drain electrode,the fourth wiring is electrically connected to the other of the second source electrode and the second drain electrode,the fifth wiring is electrically connected to the second gate electrode,the third wiring is electrically connected to the other of the electrodes of the capacitor, andthe memory cell is provided between the first driver circuit and the third driver circuit, and between the second driver circuit and the fourth driver circuit.
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Abstract
An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, a memory cell connected between the source line and the bit line, a first driver circuit electrically connected to the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is formed using a semiconductor material other than an oxide semiconductor. The second transistor is formed using an oxide semiconductor material.
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Citations
24 Claims
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1. A semiconductor device comprising:
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a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring; a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor;a first driver circuit electrically connected to the first wiring; a second driver circuit electrically connected to the second wiring and the third wiring; a third driver circuit electrically connected to the fourth wiring; and a fourth driver circuit electrically connected to the fifth wiring, wherein; the second transistor comprises an oxide semiconductor layer comprising a channel formation region, the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, the second wiring is electrically connected to one of the first source electrode and the first drain electrode, the first wiring is electrically connected to the other of the first source electrode and the second drain electrode, the fourth wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fifth wiring is electrically connected to the second gate electrode, the third wiring is electrically connected to the other of the electrodes of the capacitor, and the memory cell is provided between the first driver circuit and the third driver circuit, and between the second driver circuit and the fourth driver circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring; a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor;a first driver circuit electrically connected to the first wiring; a second driver circuit electrically connected to the second wiring and the third wiring; a third driver circuit electrically connected to the fourth wiring; and a fourth driver circuit electrically connected to the fifth wiring, wherein; the second transistor comprises an oxide semiconductor layer comprising a channel formation region, the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, the second wiring is electrically connected to one of the first source electrode and the first drain electrode, the first wiring is electrically connected to the other of the first source electrode and the second drain electrode, the fourth wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fifth wiring is electrically connected to the second gate electrode, the third wiring is electrically connected to the other of the electrodes of the capacitor, and the memory cell is provided between the first driver circuit and the fourth driver circuit, and between the second driver circuit and the third driver circuit. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring; a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor;a first driver circuit electrically connected to the first wiring and the second wiring; a second driver circuit electrically connected to the third wiring; a third driver circuit electrically connected to the fourth wiring; and a fourth driver circuit electrically connected to the fifth wiring, wherein; the second transistor comprises an oxide semiconductor layer comprising a channel formation region, the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, the third wiring is electrically connected to one of the first source electrode and the first drain electrode, the first wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fifth wiring is electrically connected to the second gate electrode, the second wiring is electrically connected to the other of the electrodes of the capacitor, and the memory cell is provided between the first driver circuit and the third driver circuit, and between the second driver circuit and the fourth driver circuit. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a first wiring, a second wiring extending across the first wiring, a third wiring, a fourth wiring, and a fifth wiring; a memory cell comprising a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor;a first driver circuit electrically connected to the first wiring and the second wiring; a second driver circuit electrically connected to the third wiring; a third driver circuit electrically connected to the fourth wiring; and a fourth driver circuit electrically connected to the fifth wiring, wherein; the second transistor comprises an oxide semiconductor layer comprising a channel formation region, the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, the third wiring is electrically connected to one of the first source electrode and the first drain electrode, the first wiring is electrically connected to the other of the second source electrode and the second drain electrode, the fifth wiring is electrically connected to the second gate electrode, the second wiring is electrically connected to the other of the electrodes of the capacitor, and the memory cell is provided between the first driver circuit and the fourth driver circuit, and between the second driver circuit and the third driver circuit. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsYamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
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Primary Examiner(s)Tran, Andrew Q
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Application NumberUS13/790,351Publication NumberTime in Patent Office347 DaysField of Search365/185.08, 365/185.21, 365/185.23, 365/185.18, 365/185.05US Class Current365/185.08CPC Class CodesG11C 11/404 with one charge-transfer ga...G11C 11/409 Read-write [R-W] circuitsG11C 16/02 electrically programmable
