Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

• US 8,654,587 B2
• Filed: 06/18/2013
• Issued: 02/18/2014
• Est. Priority Date: 08/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, ChiWeon, Chae, Donghyuk, Nam, Sang-Wan, Yun, Sung-Won
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/920,691
• Publication Number:
  US 20130279262A1
• Time in Patent Office: 245 Days
• Field of Search: 365/185.05, 365/185.17, 365/185.18, 365/185.27, 365/185.28
• US Class Current: 365/185.18
• CPC Class Codes: A62B 18/006 with pumps for forced ventilation A62B18/045 takes precedence
• CPC Class Codes: A62B 7/10 with filter elements
• CPC Class Codes: A62B 9/04 Couplings; Supporting frames
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

Claims

1. A program method of a non-volatile memory device which includes groups of memory cells sequentially provided in a direction vertical to a substrate and in which at least two strings are connected to one bit line, the program method comprising:

performing a bit line setup operation together with a channel boosting operation; and

performing a program execution operation by applying a program voltage to a selected word line,

wherein the performing a bit line setup operation includes, during a first bit line setup period, applying a power supply voltage to unselected bit lines, floating all strings of a selected memory block, and applying a pass voltage to the selected word line and unselected word lines, and

wherein the floating of the strings of the selected memory block includes applying a ground voltage to a ground selection line and to all string selection lines.

2. The program method of claim 1, wherein the performing a bit line setup operation includes, during a second bit line setup period,

setting a channel of a selected string to a ground voltage by applying a power supply voltage to a selected string selection line of the string selection lines.

3. The program method of claim 2, wherein the performing a program execution operation includes applying the program voltage to the selected word line following the second bit line setup period.

4. A program method of a non-volatile memory device which includes groups of memory cells sequentially provided in a direction vertical to a substrate and in which at least two strings are connected to one bit line, the program method comprising:

performing a bit line setup operation together with a channel boosting operation; and

performing a program execution operation by applying a program voltage to a selected word line,

wherein the performing a bit line setup operation includes, during a first bit line setup period, applying a power supply voltage to all bit lines and all string selection lines, and applying a ground voltage to a ground selection line, and

wherein the performing a bit line setup operation includes applying, during the first bit line setup period, the ground voltage to at least one unselected string selection line.

5. The program method of claim 4, wherein the performing a bit line setup operation includes, during a second bit line setup period,

applying the ground voltage to a selected bit line of the bit lines in synchronization with the applying of the ground voltage to the at least one unselected string selection line, and

applying a pass voltage to unselected word lines following the second bit line setup period.

6. The program method of claim 5, wherein the performing a program execution operation includes applying the program voltage to the selected word line following the second bit line setup period.