Hardware automatic performance state transitions in system on processor sleep and wake events

• US 8,656,196 B2
• Filed: 04/16/2013
• Issued: 02/18/2014
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: de Cesare, Josh P., Cho, Jung Wook, Takayanagi, Toshinari, Millet, Timothy J.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US13/863,554
• Publication Number:
  US 20130232364A1
• Time in Patent Office: 308 Days
• Field of Search: 713/300, 713/320, 713/323, 713/324, 455/574, 345/52, 365/227
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Claims

1. An apparatus comprising:

a plurality of components, each component included in one of a plurality of performance domains;

a power management unit comprising a plurality of configuration registers, wherein the plurality of configuration registers are programmed with data identifying performance states for the plurality of performance domains, wherein at least two performance states are identified for each performance domain of the plurality of performance domains, and wherein the power management unit is configured to establish a selected performance state of the at least two performance states in each of the plurality of performance domains responsive to an event that is asynchronous to the programming of the plurality of configuration registers.

2. The apparatus as recited in claim 1 wherein a first processor is one of the plurality of components, and wherein one of the at least two performance states identified for each performance domain is associated with a sleep state of the first processor, and wherein the event is a transition to the sleep state.

3. The apparatus as recited in claim 2 wherein another one of the at least two performance states identified for each performance domain is associated with an awake state of the first processor.

4. The apparatus as recited in claim 1 wherein the power management unit further comprises a second plurality of configuration registers, wherein the second plurality of configuration registers are programmable with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

5. The apparatus as recited in claim 4 wherein each of the second plurality of configuration registers is assigned to a respective one of the plurality of performance domains and to one of the at least two performance states.

6. The apparatus as recited in claim 5 wherein a different performance state is selected for a given performance domain by writing a different pointer to the corresponding one of the second plurality of configuration registers.

7. A method comprising:

programming a plurality of configuration registers in a power management unit of an integrated circuit with data identifying performance states for a plurality of performance domains, wherein each of a plurality of components in the integrated circuit is included in one of the plurality of performance domains, and wherein at least two performance states are identified for each performance domain of the plurality of performance domains; and

the power management unit establishing a selected performance state of the at least two performance states in each of the plurality of performance domains responsive to an event that is asynchronous to the programming of the plurality of configuration registers.

8. The method as recited in claim 7 wherein a first processor is one of the plurality of components, and wherein one of the at least two performance states identified for each performance domain is associated with a sleep state of the first processor, and wherein the event is a transition to the sleep state.

9. The method as recited in claim 8 wherein another one of the at least two performance states identified for each performance domain is associated with an awake state of the first processor.

10. The method as recited in claim 7 wherein the power management unit further comprises a second plurality of configuration registers, and the method further comprises programming the second plurality of configuration registers with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

11. The method as recited in claim 10 wherein each of the second plurality of configuration registers is assigned to a respective one of the plurality of performance domains and to one of the at least two performance states.

12. The method as recited in claim 10 further comprising:

determining that one of the at least two performance states for the one of the plurality of performance domains is to be changed to a new performance state; and

programming a corresponding one of the second plurality of configuration registers with a pointer to one of the plurality of configuration registers that stores the new performance state.

13. The method as recited in claim 12 further comprising enabling a first component in the one of the plurality of performance domains, wherein the determining is responsive to the enabling.

14. The method as recited in claim 12 further comprising disabling a first component in the one of the plurality of performance domains, wherein the determining is responsive to the disabling.

15. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed by a processor within an integrated circuit:

program a plurality of configuration registers in a power management unit of the integrated circuit with data identifying performance states for a plurality of performance domains, wherein each of a plurality of components in the integrated circuit is included in one of the plurality of performance domains, and wherein at least two performance states are identified for each performance domain of the plurality of performance domains; and

wherein the power management unit is configured to establish a selected performance state of the at least two performance states in each of the plurality of performance domains responsive to an event that is asynchronous to the execution of the plurality of instructions to program the plurality of configuration registers.

16. The non-transitory computer accessible storage medium as recited in claim 15 wherein the processor is one of the plurality of components, and wherein one of the at least two performance states identified for each performance domain is associated with a sleep state of the processor, and wherein the event is a transition to the sleep state, and wherein another one of the at least two performance states identified for each performance domain is associated with an awake state of the processor.

17. The non-transitory computer accessible storage medium as recited in claim 15 wherein the power management unit further comprises a second plurality of configuration registers, and the plurality of instructions, when executed, program the second plurality of configuration registers with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

18. The non-transitory computer accessible storage medium as recited in claim 17 wherein the plurality of instructions, when executed:

determine that one of the at least two performance states for the one of the plurality of performance domains is to be changed to a new performance state; and

program a corresponding one of the second plurality of configuration registers with a pointer to one of the plurality of configuration registers that stores the new performance state.

19. The non-transitory computer accessible storage medium as recited in claim 18 wherein the plurality of instructions, when executed, enable a first component in the one of the plurality of performance domains, and wherein the determination that one of the at least two performance states is to be changed is responsive to the enable.

20. The non-transitory computer accessible storage medium as recited in claim 18 wherein the plurality of instructions, when executed, disable a first component in the one of the plurality of performance domains, wherein the determination that one of the at least two performance states is to be changed is responsive to the disable.