System on chip breakpoint methodology

• US 8,656,221 B2
• Filed: 05/13/2010
• Issued: 02/18/2014
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Sixsou, Emmanuel, Rushinek, Elchanan, Navon, Mois
• Primary Examiner(s): BUTLER, SARAI E
• Application Number:
  US12/779,422
• Publication Number:
  US 20110219217A1
• Time in Patent Office: 1,377 Days
• Field of Search: 714/34, 714/25, 714/10, 714/48, 714/35
• US Class Current: 714/34
• CPC Class Codes: G06F 11/362 Software debugging

Abstract

A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other than the computing element driving the breakpoint event.

Claims

1. A system-on-chip (SoC) with debugging capability, the system-on-chip comprising:

a central processing unit (CPU);

a plurality of computing elements operatively connected to said CPU, wherein said computing elements include a hardware state machine which varies among a plurality of states, wherein the CPU is configured to program said computing elements with task descriptors and said computing elements are configured to receive said task descriptors to perform a computation, wherein the task descriptors include a field which specifies a breakpoint state of the computing element; and

a system level event status register (ESR) operatively attached to and accessible by said CPU and said computing elements;

wherein each of said computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state, wherein the computing element is configured to drive a breakpoint event to said event status register (ESR) if the present state of the computing element is the breakpoint state;

wherein each of said computing elements has a halt logic unit operatively attached thereto, wherein said halt logic unit is configured to halt operation of the computing element, wherein said ESR is configurable to drive a breakpoint event to said halt logic units so that at least one of the computing elements is halted other than the computing element driving said breakpoint event.

2. The system-on-chip (SoC), according to claim 1, further comprising:

a debug control register (DCR) operatively attached to and accessible by the CPU and the computing elements;

wherein said DCR provides control inputs to said halt logic units.

3. The system-on-chip (SoC) according to claim 2 wherein said control inputs of said DCR are configurable so that when a single computing element drives said breakpoint event, based on said control inputs from said DCR, all the computing elements are halted except said single computing element.

4. The system-on-chip (SoC) according to claim 2 wherein said control inputs of said DCR are configurable so that when a single computing element drives said breakpoint event, and based on said control inputs from said DCR, all the computing elements are halted.

5. The system-on-chip (SoC) according to claim 2 wherein said control inputs of said DCR are configurable so that when a single computing element drives said breakpoint event, and based on said control inputs from said DCR, some but not all of the computing elements are halted.

6. A method for debugging a system on a chip (SoC), the SoC including a central processing unit (CPU), a plurality of computing elements operatively connected to said CPU, a system level event status register (ESR) operatively attached to and accessible by the CPU and the computing elements, the method comprising:

reading task descriptors by the computing elements received from the CPU;

initiating a computation by the computing elements as specified in the task descriptors, wherein said computing elements include a hardware state machine which varies among a plurality of states, wherein the task descriptors include a field which specifies a breakpoint state of the computing elements;

comparing the present state of the computing elements to the breakpoint state;

upon the present state of the computing elements being the breakpoint state, driving a breakpoint event by the computing element to the event status register (ESR), thereby storing the break point event in the event status register (ESR);

driving outputs from the ESR to the computing elements;

and

halting operation of at least one of the computing elements other than the computing element driving said breakpoint event.

7. The method, according to claim 6, further comprising:

configuring a debug control register (DCR) operatively attached to and accessible by the CPU and the computing elements; and

performing said halting based on the configuration of said DCR.

8. The method, according to claim 6, wherein said halting is for any of the computing elements selectably either:

at the end of one of the computations or during one of the computations.

9. The method, according to claim 6, further comprising:

upon said halting, debugging at least one of the computing elements by the CPU.

10. The method, according to claim 6, further comprising:

accessing the ESR to determine which of the computing elements triggered said break event.

11. The method, according to claim 6, wherein a system level event status register (ESR) is operatively attached to and accessible by the CPU and the computing elements, the method further comprising:

accessing the ESR to determine which computing elements are halted as a result of break event.

12. The method, according to claim 6, prior to said halting, the method further comprising:

configuring said halting based on control inputs.

13. The method, according to claim 12, wherein said driving said breakpoint event is from a single computing element, the method further comprising:

based on said control inputs, halting all the computing elements except the computing element driving said breakpoint event.

14. The method, according to claim 12, wherein said driving said breakpoint event is from a single computing element, the method further comprising:

based on said control inputs, halting all the computing elements.

15. The method, according to claim 12, wherein said driving said breakpoint event is from a single computing element, the method further comprising:

based on said control inputs, some but not all of the computing elements are halted.

16. The method, according to claim 6, wherein said halting operation of said at least one of the computing elements is performed immediately upon receiving a halt signal during the computation.