Based device risk assessment

• US 8,656,323 B2
• Filed: 02/17/2012
• Issued: 02/18/2014
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Park, Allen, Cho, SungChan, Saville, Barry, Jin, Youseung
• Primary Examiner(s): Thompson, A. M.
• Application Number:
  US13/399,805
• Publication Number:
  US 20120216169A1
• Time in Patent Office: 732 Days
• Field of Search: None
• US Class Current: 716/56
• CPC Class Codes: G01N 2021/8883 involving the calculation of gauges, generating models
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/32182 If state of tool, product deviates from standard, adjust system, feedback
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01J 37/26 Electron or ion microscopes; Electron or ion diffraction tubes
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The process for designed based assessment includes the following steps. First, the process defines multiple patterns of interest (POIs) utilizing design data of a device and then generates a design based classification database. Further, the process receives one or more inspection results. Then, the process compares the inspection results to each of the plurality of POIs in order to identify occurrences of the POIs in the inspection results. In turn, the process determines yield impact of each POI utilizing process yield data and monitors a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device. Finally, the process determines a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons.

Claims

1. A method for providing risk assessment or yield correlation in a memory device, comprising:

defining a plurality of regions based on one or more functional areas of a device as identified in design data of the device;

performing one or more inspection processes on the one or more defined regions;

identifying one or more dies of the one or more defined regions falling below a predetermined control limit by analyzing the inspection data from the one or more inspection processes to determine whether a defect frequency of the one or more defined regions of the one or more dies is below the predetermined control limit; and

identifying regions impacting yield loss by comparing the one or more dies falling below the predetermined control limit to inline data for each of the regions.

2. The method of claim 1, wherein the one or more functional areas of the memory device comprise:

at least one of a main area of the memory device, a redundant memory area of the memory device, and a dummy area of the memory device.

3. The method of claim 1, wherein the one or more inspection processes comprise:

at least one of dark field inspection and bright field inspection.

4. The method of claim 1, wherein the predetermined control limit is user established.