Capacitive micromachined ultrasonic transducer

• US 8,658,453 B2
• Filed: 12/19/2006
• Issued: 02/25/2014
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Sonetics Ultrasound, Inc.
• Original Assignee: Sonetics Ultrasound, Inc.
• Inventors: Lemmerhirt, David F., Rich, Collin A.
• Primary Examiner(s): TORNOW, MARK W
• Application Number:
  US11/612,659
• Publication Number:
  US 20070167812A1
• Time in Patent Office: 2,625 Days
• Field of Search: 438/53, 438/50, 257/415
• US Class Current: 438/53
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type

Abstract

The first integrated circuit/transducer device 36 of the handheld probe includes CMOS circuits 110 and cMUT elements 112. The cMUT elements 112 function to generate an ultrasonic beam, detect an ultrasonic echo, and output electrical signals, while the CMOS circuits 110 function to perform analog or digital operations on the electrical signals generated through operation of the cMUT elements 112. The manufacturing method for the first integrated circuit/transducer device 36 of the preferred embodiment includes the steps of depositing the lower electrode S102; depositing a sacrificial layer S104; depositing a dielectric layer S106; removing the sacrificial layer S108, followed by the steps of depositing the upper electrode S110 and depositing a protective layer on the upper electrode S112.

Claims

1. A method of producing an integrated circuit/transducer device including a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit over a CMOS circuit region on the substrate and a capacitive micromachined ultrasonic transducer (cMUT) element over a cMUT element region on the substrate, the method comprising:

depositing a first layer over both the CMOS circuit region and the cMUT element region that;

forms a lower electrode over the cMUT element region; and

forms a layer over the CMOS circuit region;

b) depositing a sacrificial layer after step a);

c) depositing a dielectric layer over the CMOS circuit and cMUT element regions after step b);

d) removing the sacrificial layer to form a cavity after step c); and

e) depositing a second layer over both the CMOS circuit region and the cMUT element region after step d) that;

forms an upper electrode over the cMUT element region; and

forms a layer over the CMOS circuit region.

2. The method of claim 1, further comprising the steps of:

fabricating a second capacitive micromachined ultrasonic transducer (cMUT) element on the substrate, wherein the second cMUT element includes a second lower electrode, a second dielectric layer, a second sacrificial layer located between the lower electrode and the dielectric layer, and a second upper electrode on the second dielectric layer; and

removing the sacrificial layer of the second cMUT element thereby defining a cavity between the lower electrode and the dielectric layer.

3. The method of claim 2, wherein the second layer of step e) further forms the second upper electrode of the second cMUT element.

4. The method of claim 2, further comprising the step of depositing a protective layer on the upper electrodes of the first and second cMUT elements.

5. The method of claim 4, further comprising thinning the protective layer to produce the capacitive micromachined ultrasonic transducer structure.

6. The method of claim 2, wherein the second cMUT is fabricated concurrently with the CMOS circuit and the first cMUT in the same fabrication process, such that the second lower electrode, the second dielectric layer, and the second upper electrode are layers used in the fabrication of the CMOS circuit and the first cMUT.

7. The method of claim 1, further comprising depositing a protective layer over the upper electrode.

8. The method of claim 7, wherein depositing a protective layer over the upper electrode comprises depositing a protective layer over the cMUT element region and the CMOS circuit region.

9. The method of claim 7, further comprising thinning the protective layer.

10. The method of claim 7, wherein the protective layer comprises oxynitride.

12. The method of claim 1, wherein the layer formed over the CMOS circuit region in step e) extends through the dielectric layer to connect two elements within the CMOS circuit.

13. The method of claim 1, wherein the second layer comprises metal.

14. The method of claim 1, wherein the first layer comprises doped polysilicon.

15. The method of claim 1, wherein sacrificial layer is deposited over the cMUT element region in step b).

16. The method of claim 3, wherein the upper electrode is metal.

17. The method of claim 2, wherein the upper electrodes of the first and second cMUT elements are electrically coupled.

18. The method of claim 1, wherein the cMUT element region and the CMOS element region are distinct regions on the substrate.

11. The method of step 1, further comprising depositing a dielectric layer over the CMOS circuit region and cMUT element region between steps a) and b).