Semiconductor device and fabrication method thereof

• US 8,658,487 B2
• Filed: 11/17/2011
• Issued: 02/25/2014
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liao, Duan-Quan, Hsu, Shih-Chieh, Chen, Yi-Kun, Tey, Ching-Hwa
• Primary Examiner(s): Fan, Michele
• Application Number:
  US13/298,395
• Publication Number:
  US 20130130460A1
• Time in Patent Office: 831 Days
• Field of Search: 438/199, 438/229, 438/275, 438/369, 438/197, 438/294, 438/299, 257/368, 257/E21.409, 257/E29.242, 257/E21.444, 227/368, 227/E21.409, 227/E29.242, 227/E21.444
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate;

providing a second dummy gate simultaneously with the provision of the first dummy gate, wherein the second dummy gate has a second high-k gate insulator layer, a second composite sacrificial layer, and a second dummy gate electrode sequentially stacked on the substrate;

removing the first dummy gate electrode to expose the first composite sacrificial layer;

removing the second dummy gate electrode simultaneously with the step of removing the first dummy gate electrode to expose the second composite sacrificial layer;

forming a first patterned photo-resist layer to cover the exposed second composite sacrificial layer,

removing the first composite sacrificial layer;

forming a first work function layer on the first high-k gate insulator layer; and

forming a first metal gate electrode on the first work function layer.

2. The method for fabricating the semiconductor device according to claim 1, wherein the formation of the first work function layer is carried out after the first patterned photo-resist, layer is removed such that exposed second composite sacrificial layer is covered by the first work function layer.

3. The method for fabricating the semiconductor device according to claim 2, further comprising:

forming a second patterned photo-resist layer to cover a portion of the first work function layer which covers the first high-k gate insulator layer;

performing an etching process to remove portions of the first work function layer and the second composite sacrificial layer that are not covered by the second patterned photo-resist layer;

forming a second work function layer on the first high-k gate insulator layer and the second high-k gate insulator layer, after the second patterned photo-resist layer is removed; and

forming a second metal gate electrode on the second work function layer simultaneously with the formation of the first metal gate electrode.

4. The method for fabricating the semiconductor device according to claim 3, wherein the first work function layer is made of titanium nitride (TiN);

and the second work function layer is made of titanium-aluminum alloy (TiAl).

5. The method for fabricating the semiconductor device according to claim 1, wherein the first composite sacrificial, layer and the second composite sacrificial layer both comprise:

a patterned silicon-containing sacrificial layer, formed on the first high-k gate insulator layer and the second high-k gate insulator layer; and

a patterned metal nitride sacrificial layer, formed on the patterned silicon-containing sacrificial layer.

6. The method for fabricating the semiconductor device according to claim 5, wherein the metal nitride sacrificial layer is made of TiN or tantalum nitride (TaN).

7. The method for fabricating the semiconductor device according to claim 5, wherein the first dummy gate and the second dummy gate further comprise a patterned TiN capping layer formed beneath the patterned silicon-containing sacrificial layer and over the first high-k gate insulator layer and the second high-k gate insulator layer.

8. The method for fabricating the semiconductor device according to claim 5, wherein the step of removing the first composite sacrificial layer comprises:

applying an ammonia-containing agent to remove a portion of the patterned metal nitride sacrificial layer, such that a portion of the patterned silicon-containing sacrificial layer that overlies the first high-k gate insulator layer is exposed; and

applying a chloride-containing agent to remove the exposed portion of the patterned silicon-containing sacrificial layer.

9. The method for fabricating the semiconductor device according to claim 1, further comprising steps of using the first dummy gate and the second dummy gate as a mask to form a first source/drain structure and a second source/drain structure in the substrate adjacent to the first dummy gate structure and the second dummy gate structure, respectively.

10. A method for fabricating a complementary metal-oxide semiconductor (CMOS) transistor comprising:

providing a first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on an N well region of a substrate;

providing a second dummy gate simultaneously with the provision of the first dummy gate, wherein the second dummy gate has a second high-k gate insulator layer, a second composite sacrificial layer, and a second dummy gate electrode sequentially stacked on a P well region of the substrate;

removing the first dummy gate electrode and the second dummy gate electrode to expose the first composite sacrificial layer and the second composite sacrificial layer;

forming a first patterned photo-resist layer to cover the exposed second composite sacrificial layer;

removing the first composite sacrificial layer to expose the first high-k gate insulator layer;

forming a first work function layer on the first high-k gate insulator layer and the exposed second composite sacrificial layer, after the first patterned photo-resist layer is removed;

forming a second patterned photo-resist layer to cover a portion of the first work function layer which covers the first high-k gate insulator layer;

performing an etching process to remove portions of the first work function layer and the second composite sacrificial layer that are not covered by the second patterned photo-resist layer;

forming a second work function layer on the first high-k gate insulator layer and the second high-k gate insulator layer, after the second patterned photo-resist layer is removed;

forming a first metal gate electrode on the first work function layer; and

forming a second metal gate electrode on the second work function layer simultaneously with the formation of the first metal gate electrode.