Method for dual work function metal gate CMOS with selective capping

• US 8,658,489 B2
• Filed: 08/15/2013
• Issued: 02/25/2014
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chambers, James Joseph, Niimi, Hiroaki
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US13/968,074
• Publication Number:
  US 20130337656A1
• Time in Patent Office: 194 Days
• Field of Search: 438/199, 438/585, 438/588, 438/652, 257/369, 257/407, 257/E27.062, 257/E27.108
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.

Claims

1. A method of forming a device, comprising the steps of:

providing a semiconductor body having a NMOS gate stack, a PMOS gate stack, and an oxide layer formed thereon, wherein the NMOS gate stack comprises a first gate dielectric, a first mid-gap metal gate, and a first dummy poly layer and the PMOS gate stack comprises a second gate dielectric, a second mid-gap metal gate, and a second dummy poly layer;

removing the first dummy poly layer and the second dummy poly layer;

performing a low temperature oxidation to incorporate oxygen into the first mid-gate metal gate and the second mid-gap metal gate;

depositing a first cap layer over the NMOS gate stack and the PMOS gate stack;

removing the first cap layer from one of the NMOS gate stack and PMOS gate stack;

depositing a second cap layer over both the NMOS gate stack and the PMOS gate stack, wherein one of the first cap layer and the second cap layer comprise a low oxygen affinity and high work function material and the other comprises a high oxygen affinity and low work function material such that oxygen is scavenged from the first mid-gap metal gate; and

after depositing the second cap layer, annealing the device to incorporate low work function material into the first mid-gap metal gate at an interface between the first mid-gap metal gate and the first gate dielectric.

2. The method of claim 1, wherein the step of removing the first cap layer from one of the NMOS gate stack and the PMOS gate stack, removes the first cap layer from the NMOS gate stack, and wherein the first cap layer comprises the low oxygen affinity and high work function material while the second cap layer comprises the high oxygen affinity and low work function material.

3. The method of claim 1, wherein the step of removing the first cap layer from one of the NMOS gate stack and the PMOS gate stack, removes the first cap layer from the PMOS gate stack, and wherein the first cap layer comprises the high oxygen affinity and low work function material while the second cap layer comprises the low oxygen affinity and high work function material.