Semiconductor device

• US 8,659,015 B2
• Filed: 02/23/2012
• Issued: 02/25/2014
• Est. Priority Date: 03/04/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yoneda, Seiichi
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US13/403,311
• Publication Number:
  US 20120223304A1
• Time in Patent Office: 733 Days
• Field of Search: 235/492, 257/43, 327/306
• US Class Current: 257/43
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H03C 2200/0029 Memory circuits, e.g. ROMs, RAMs, EPROMs, latches, shift registers
• CPC Class Codes: H03H 7/1741 Comprising typical LC combinations, irrespective of presence and location of additional resistors when resistors are present, also classify in H03H7/06 - H03H7/07
• CPC Class Codes: H03J 1/00 Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
• CPC Class Codes: H03J 3/10 Circuit arrangements for fine tuning, e.g. bandspreading

Abstract

A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor.

Claims

1. A semiconductor device comprising:

a coil;

a capacitor whose first terminal is electrically connected to a first terminal of the coil and whose second terminal is electrically connected to a second terminal of the coil;

a passive element whose first terminal is electrically connected to the first terminal of the coil;

a first transistor whose first terminal is electrically connected to a second terminal of the passive element and whose second terminal is electrically connected to the second terminal of the coil;

a second transistor whose first terminal is electrically connected to a gate of the first transistor;

a second capacitor whose first terminal is electrically connected to the gate of the first transistor;

a third transistor whose first terminal is electrically connected to the first terminal of the coil and whose second terminal is electrically connected to a second terminal of the second capacitor; and

a load whose first terminal is electrically connected to the second terminal of the third transistor and whose second terminal is electrically connected to the second terminal of the coil,

wherein the second transistor comprises a semiconductor layer including a channel, the channel including an oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the passive element is one of a capacitor and a coil.

3. The semiconductor device according to claim 1, further comprising:

a second passive element whose first terminal is electrically connected to the first terminal of the coil; and

a fourth transistor whose first terminal is electrically connected to a second terminal of the second passive element and whose second terminal is electrically connected to the second terminal of the coil.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises an In—

Ga—

Zn-based oxide semiconductor.

5. The semiconductor device according to claim 1, further comprising a rectifier circuit whose first terminal is electrically connected to the first terminal of the coil and whose second terminal is electrically connected to the second terminal of the coil.

6. A semiconductor device comprising:

a coil;

a capacitor electrically connected to the coil in parallel;

a passive element that forms a resonance circuit with the coil and the capacitor by being electrically connected to the coil and the capacitor in parallel;

a first field effect transistor capable of controlling whether the passive element is electrically connected to the coil and the capacitor in parallel or not; and

a memory circuit,

wherein the memory circuit includes a second field effect transistor that comprises a semiconductor layer including a channel, the channel including an oxide semiconductor,

wherein a voltage of a gate of the first field effect transistor is set in accordance with a voltage of one of a source and a drain of the second field effect transistor, and

wherein a data signal is input to the other one of the source and the drain of the second field effect transistor.

7. The semiconductor device according to claim 6, wherein the passive element is one of a capacitor and a coil.

8. The semiconductor device according to claim 6, further comprising:

a second passive element whose first terminal is electrically connected to the first terminal of the coil; and

a third transistor whose first terminal is electrically connected to a second terminal of the second passive element and whose second terminal is electrically connected to the second terminal of the coil.

9. The semiconductor device according to claim 6, wherein the oxide semiconductor comprises an In—

Ga—

Zn-based oxide semiconductor.

10. The semiconductor device according to claim 6, further comprising a rectifier circuit whose first terminal is electrically connected to the first terminal of the coil and whose second terminal is electrically connected to the second terminal of the coil.

11. A semiconductor device comprising:

a coil;

a capacitor electrically connected to the coil in parallel;

a passive element that forms a resonance circuit with the coil and the capacitor by being electrically connected to the coil and the capacitor in parallel;

a first field effect transistor capable of controlling whether the passive element is electrically connected to the coil and the capacitor in parallel or not; and

a memory circuit,

wherein the memory circuit includes a second field effect transistor that comprises a semiconductor layer including a channel, the channel including an oxide semiconductor,

wherein one of a source and a drain of the second field effect transistor is electrically connected to a gate of the first field effect transistor, and

wherein the memory circuit includes;

a second capacitor whose first electrode is electrically connected to the gate of the first field effect transistor;

a third field effect transistor, wherein one of a source and a drain of the third field effect transistor is electrically connected to a second electrode of the second capacitor and a voltage of the other one of the source and the drain of the third field effect transistor is changed in accordance with an electric wave received by the coil; and

a fourth field effect transistor that comprises a semiconductor layer including a channel, the channel including an oxide semiconductor, wherein one of a source and a drain of the fourth field effect transistor is electrically connected to a gate of the third field effect transistor.

12. The semiconductor device according to claim 11, wherein a data signal is input to the other one of the source and the drain of the second field effect transistor.

13. The semiconductor device according to claim 11,

wherein a first data signal is input to the other one of the source and the drain of the second field effect transistor, and

wherein a second data signal is input to the other one of the source and the drain of the fourth field effect transistor.

14. The semiconductor device according to claim 11, wherein the passive element is one of a capacitor and a coil.

15. The semiconductor device according to claim 11, further comprising:

a second passive element whose first terminal is electrically connected to the first terminal of the coil; and

a third transistor whose first terminal is electrically connected to a second terminal of the second passive element and whose second terminal is electrically connected to the second terminal of the coil.

16. The semiconductor device according to claim 11, wherein each of the oxide semiconductors of the second field effect transistor and the oxide semiconductor of the fourth field effect transistor comprises an In—

Ga—

Zn-based oxide semiconductor.

17. The semiconductor device according to claim 11, further comprising a rectifier circuit whose first terminal is electrically connected to the first terminal of the coil and whose second terminal is electrically connected to the second terminal of the coil.

18. A semiconductor device comprising:

an antenna;

a capacitor whose first terminal is electrically connected to a first terminal of the antenna and whose second terminal is electrically connected to a second terminal of the antenna;

a passive element whose first terminal is electrically connected to the first terminal of the antenna;

a first transistor whose first terminal is electrically connected to a second terminal of the passive element and whose second terminal is electrically connected to the second terminal of the antenna;

a second transistor whose first terminal is electrically connected to a gate of the first transistor;

a second capacitor whose first terminal is electrically connected to the gate of the first transistor;

a third transistor whose first terminal is electrically connected to the first terminal of the antenna and whose second terminal is electrically connected to a second terminal of the second capacitor; and

a load whose first terminal is electrically connected to the second terminal of the third transistor and whose second terminal is electrically connected to the second terminal of the antenna,

wherein the second transistor comprises a semiconductor layer including a channel, the channel including an oxide semiconductor.

19. The semiconductor device according to claim 18, wherein the passive element is one of a capacitor and a coil.

20. The semiconductor device according to claim 18, further comprising:

a second passive element whose first terminal is electrically connected to the first terminal of the antenna; and

a fourth transistor whose first terminal is electrically connected to a second terminal of the second passive element and whose second terminal is electrically connected to the second terminal of the antenna.

21. The semiconductor device according to claim 18, wherein the oxide semiconductor comprises an In—

Ga—

Zn-based oxide semiconductor.

22. The semiconductor device according to claim 18, further comprising a rectifier circuit whose first terminal is electrically connected to the first terminal of the antenna and whose second terminal is electrically connected to the second terminal of the antenna.