Thin film transistor, method of manufacturing the same and flat panel display device having the same
First Claim
Patent Images
1. A flat panel display device, comprising:
- a first substrate having disposed thereon;
first and second conductive lines, the first conductive lines disposed to cross the second conductive lines,a plurality of pixels, each of the plurality of pixels having a first electrode and being defined by the first and second conductive lines, anda plurality of thin film transistors electrically coupled to the first electrodes to control signals supplied to the pixels, respectively;
a second substrate having a second electrode formed thereon; and
a liquid crystal layer disposed in a sealed space between the first and second electrodes,wherein each of the thin film transistors comprises;
source and drain electrodes formed on the first substrate, one of the source and drain electrodes electrically coupled to one of the first and second conductive lines, and the other of the source and drain electrodes electrically coupled to the first electrode,an active layer formed of an oxide semiconductor and formed to at least partially overlap both the source and drain electrodes,a gate insulating layer formed on the first substrate to cover the active layer and the source and drain electrodes,a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer, the gate electrode electrically connected to the other of the first and second conductive lines, andan interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV,wherein a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer.
0 Assignments
0 Petitions
Accused Products
Abstract
A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.
33 Citations
8 Claims
-
1. A flat panel display device, comprising:
-
a first substrate having disposed thereon; first and second conductive lines, the first conductive lines disposed to cross the second conductive lines, a plurality of pixels, each of the plurality of pixels having a first electrode and being defined by the first and second conductive lines, and a plurality of thin film transistors electrically coupled to the first electrodes to control signals supplied to the pixels, respectively; a second substrate having a second electrode formed thereon; and a liquid crystal layer disposed in a sealed space between the first and second electrodes, wherein each of the thin film transistors comprises; source and drain electrodes formed on the first substrate, one of the source and drain electrodes electrically coupled to one of the first and second conductive lines, and the other of the source and drain electrodes electrically coupled to the first electrode, an active layer formed of an oxide semiconductor and formed to at least partially overlap both the source and drain electrodes, a gate insulating layer formed on the first substrate to cover the active layer and the source and drain electrodes, a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer, the gate electrode electrically connected to the other of the first and second conductive lines, and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV, wherein a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer. - View Dependent Claims (2, 3, 4)
-
-
5. A flat panel display device, comprising:
-
a first substrate having an organic light emitting device, gate and data lines, and a thin film transistor formed thereon, the organic light emitting device including a first electrode, an organic thin film layer, and a second electrode, and the thin film transistor controlling operation of the organic light emitting device; and a second substrate disposed opposite to the first substrate, wherein the thin film transistor comprises; source and drain electrodes formed on the first substrate, one of the source and drain electrodes electrically connected to one of the data lines, an active layer formed of an oxide semiconductor and formed to at least partially overlap both the source and drain electrodes, a gate insulating layer formed on the substrate to cover the active layer and the source and drain electrodes, a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer, the gate electrode electrically connected to one of the gate lines, and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV, wherein a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer. - View Dependent Claims (6, 7, 8)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
-
Original AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
-
InventorsKim, Min-Kyu, Jeong, Jong-Han, Ahn, Tae-Kyung, Jeong, Jae-Kyeong, Mo, Yeon-Gon, Park, Jin-Seong, Chung, Hyun-Joong, Kim, Kwang-Suk, Yang, Hui-Won
-
Primary Examiner(s)Luu, Chuong A
-
Assistant Examiner(s)Doan, Nga
-
Application NumberUS13/889,752Publication NumberTime in Patent Office293 DaysField of Search257/43, 257/258, 257/646, 257/E29.094, 257/E21.476, 438/104, 438/149, 438/158US Class Current257/43CPC Class CodesH01L 29/78606 with supplementary region o...H01L 29/7869 having a semiconductor body...
