Array substrate and method of fabricating the same

• US 8,659,017 B2
• Filed: 06/20/2013
• Issued: 02/25/2014
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ryoo, Chang-Il, Seo, Hyun-Sik, Bae, Jong-Uk
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US13/923,019
• Publication Number:
  US 20130277673A1
• Time in Patent Office: 250 Days
• Field of Search: 257/43, 257/59
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the array substrate includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other; source and drain electrodes formed on the etch prevention layer; a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and a pixel electrode formed on the passivation layer and through the contact hole.

Claims

1. An array substrate for a display device, the array substrate comprising:

a gate electrode formed on a substrate;

a gate insulating layer formed on the gate electrode;

an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other;

source and drain electrodes formed on the etch prevention layer;

a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and

a pixel electrode formed on the passivation layer and through the contact hole.

2. The array substrate according to claim 1, wherein ends of the source and drain electrodes are aligned with the ends of the etch prevention layer.