Semiconductor device

• US 8,659,074 B2
• Filed: 01/08/2008
• Issued: 02/25/2014
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US11/971,123
• Publication Number:
  US 20080164516A1
• Time in Patent Office: 2,240 Days
• Field of Search: 257/328, 257/330, 257/331, 257/341, 257/342, 257/492, 257/493, 257/E29.021, 257/E29.131, 257/E29.201, 257/E29.256, 257/E29.257, 257/E29.26, 257/E29.262
• US Class Current: 257/329
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.

Claims

1. A semiconductor device comprising:

one or more first trenches which include a gate electrode, said gate electrode being capacitively coupled to a semiconductor material to control conduction therethrough; and

one or more second trenches, interspersed with said first trenches, and each having intentionally introduced spatially fixed net charge in dielectric material therein on sidewalls thereof;

wherein said second trenches at least partially balance the net charge in depleted regions of said semiconductor material, when said semiconductor material is depleted.

2. The semiconductor active device of claim 1, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches.

3. The semiconductor active device of claim 1, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches, and said ions have a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

4. The semiconductor active device of claim 1, wherein said intentionally introduced spatially fixed net charge comprises immobile ions having a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

5. The semiconductor active device of claim 1, wherein said semiconductor material is silicon.

6. A semiconductor active device comprising:

one or more first trenches which each include a gate electrode, said gate electrode being coupled to a first-conductivity-type semiconductor body to control inversion thereof, and thereby allow or deny passage of majority carriers from a second-conductivity-type source region though said first-conductivity-type semiconductor body, and a semiconductor drift region, to a second-conductivity-type drain region; and

one or more second trenches which are interspersed with said first trenches, and which include intentionally introduced spatially fixed net charge, in dielectric material therein, which is located in proximity to sidewalls of said trenches, and which is capacitively coupled to at least part of said semiconductor drift region;

wherein said second trenches at least partially balance the net charge in depleted portions of said semiconductor drift region, when such depletion occurs.

7. The semiconductor active device of claim 6, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches.

8. The semiconductor active device of claim 6, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches, and said ions have a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

9. The semiconductor active device of claim 6, wherein said intentionally introduced spatially fixed net charge comprises immobile ions having a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

10. The semiconductor active device of claim 6, wherein said first-conductivity-type semiconductor body is p type, and said majority carriers are electrons.

11. The semiconductor active device of claim 6, wherein said semiconductor drift region comprises silicon.

12. A semiconductor active device comprising:

one or more first insulated trenches which each include a respective gate electrode which is capacitively coupled to a first-conductivity-type semiconductor body to control inversion thereof, and thereby allow or deny passage of majority carriers from a second-conductivity-type source region though said first-conductivity-type semiconductor body, and a semiconductor drift region, to a second-conductivity-type drain region; and

one or more second insulated trenches which are interspersed with and deeper than said first trenches, and which include intentionally introduced spatially fixed net charge, in dielectric material therein, which is located in proximity to sidewalls of said trenches, and which is capacitively coupled to at least part of said semiconductor drift region and said first-conductivity-type semiconductor body;

wherein said second trenches at least partially balance the net charge in depleted portions of said semiconductor drift region, when such depletion occurs.

13. The semiconductor active device of claim 12, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches.

14. The semiconductor active device of claim 12, wherein said intentionally introduced spatially fixed net charge comprises immobile ions inside the dielectric material on sidewalls of said one or more second trenches, and said ions have a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

15. The semiconductor active device of claim 12, wherein said intentionally introduced spatially fixed net charge comprises immobile ions having a spatial distribution which generally corresponds to implantation through at least one sidewall of each said one or more second trenches.

16. The semiconductor active device of claim 12, wherein said first-conductivity-type semiconductor body is p type, and said majority carriers are electrons.

17. The semiconductor active device of claim 12, wherein said semiconductor drift region comprises silicon.