Semiconductor device and method of manufacturing the same

• US 8,659,078 B2
• Filed: 03/10/2013
• Issued: 02/25/2014
• Est. Priority Date: 08/09/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuura, Hitoshi, Nakazawa, Yoshito, Kachi, Tsuyoshi, Yatsuda, Yuji
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/792,134
• Publication Number:
  US 20130187223A1
• Time in Patent Office: 352 Days
• Field of Search: 257/330, 257/332, 257/E29.257, 257/E29.26, 257/E27.091
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Claims

1. A semiconductor device including a power MOSFET and a Schottky barrier diode, comprising:

a semiconductor substrate including a first region for the power MOSFET and a second region for the Schottky barrier diode;

a first impurity region of a first conductivity type formed in the first region of the semiconductor substrate and constituting a drain region of the power MOSFET;

a second impurity region of a second conductivity type opposite to the first conductivity type formed in the first impurity region and constituting a channel region of the power MOSFET;

a third impurity region of the first conductivity type formed in the second impurity region and constituting a source region of the power MOSFET;

a first trench formed in the first region of the semiconductor substrate such that the first trench penetrates through the third and second impurity regions and such that a bottom of the first trench is located inside the first impurity region;

a gate electrode of the power MOSFET embedded in the first trench;

a fourth impurity region of the first conductivity type formed in the second region of the semiconductor substrate and constituting a cathode of the Schottky barrier diode; and

a first conductive film formed on the fourth impurity region and constituting an anode of the Schottky barrier diode,

wherein an impurity concentration of the fourth impurity region is lower than an impurity concentration of the first impurity region,

wherein a second trench is formed in the fourth impurity region,

wherein a depth of the second trench is shallower than a depth of the first trench, and

wherein the first conductive film is formed inside the second trench.

2. A semiconductor device according to the claim 1,

wherein the first conductive film is formed of a first silicide film.

3. A semiconductor device according to the claim 2,

wherein a second silicide film is formed on a surface of the gate electrode and is formed by the same step as the first silicide film.

4. A semiconductor device according to the claim 1,

wherein a third trench is formed in the first region of the semiconductor substrate such that the third trench penetrates through the third impurity region and such that a bottom of the third trench is located inside the second impurity region,

wherein a second conductive film is formed inside the third trench to connect with the third and second impurity regions, and

wherein the third trench is formed by the same step as the second trench.

5. A semiconductor device according to the claim 1,

wherein the first conductivity type is an n-type, and

wherein the second conductivity type is a p-type.

6. A semiconductor device including a power MOSFET and a Schottky barrier diode, comprising:

a semiconductor substrate including a first region for the power MOSFET, a second region for the Schottky barrier diode, and a third region for a gate wire extension;

a first impurity region of a first conductivity type formed in the first region of the semiconductor substrate and constituting a drain region of the power MOSFET;

a second impurity region of a second conductivity type opposite to the first conductivity type formed in the first impurity region and constituting a channel region of the power MOSFET;

a third impurity region of the first conductivity type formed in the second impurity region and constituting a source region of the power MOSFET;

a well region of the second conductivity type formed in the third region of the semiconductor substrate;

a first trench having portions formed in the first and third regions of the semiconductor substrate, respectively, such that a portion of the first trench in the first region penetrates through the third and second impurity regions, such that a bottom of the portion of the first trench in the first region is located inside the first impurity region, such that a portion of the first trench in the third region penetrates through the well region and such that a bottom of the portion of the first trench in the third region is located inside the well region;

a gate electrode of the power MOSFET embedded in the first trench;

a gate wire formed over the third region of the semiconductor substrate and electrically connected with the gate electrode;

a fourth impurity region of the first conductivity type formed in the second region of the semiconductor substrate and constituting a cathode of the Schottky barrier diode; and

a first conductive film formed on the fourth impurity region and constituting an anode of the Schottky barrier diode,

wherein an impurity concentration of the fourth impurity region is lower than an impurity concentration of the first impurity region,

wherein a depth of the well region is deeper than a depth of the first trench, and

wherein a depth of the second impurity region is shallower than a depth of the first trench.

7. A semiconductor device according to the claim 6,

wherein the third impurity region is not formed in the well region.

8. A semiconductor device according to the claim 6,

wherein the fourth impurity region is also formed in the third region, and

wherein the well region is formed in the fourth impurity region of the third region.

9. A semiconductor device according to the claim 6,

wherein the first conductive film is formed of a first silicide film.

10. A semiconductor device according to the claim 9,

wherein a second silicide film is formed on a surface of the gate electrode and a surface of the gate wire, and is formed by the same step as the first silicide film.

11. A semiconductor device according to the claim 6,

wherein a second trench is formed in the fourth impurity region,

wherein a depth of the second trench is shallower than a depth of the first trench, and

wherein the first conductive film is formed inside the second trench.

12. A semiconductor device according to the claim 11,

wherein a third trench is formed in the first region of the semiconductor substrate such that the third trench penetrates through the third impurity region and such that a bottom of the third trench is located inside the second impurity region,

wherein a second conductive film is formed inside the third trench to connect with the third and second impurity regions, and

wherein the third trench is formed by the same step as the second trench.

13. A semiconductor device according to the claim 6,

wherein the first conductivity type is an n-type, and

wherein the second conductivity type is a p-type.