Transistor device and method for manufacturing the same

• US 8,659,079 B2
• Filed: 05/29/2012
• Issued: 02/25/2014
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Liao, Wei-Ming, Wu, Tieh-Chiang
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/481,975
• Publication Number:
  US 20130320442A1
• Time in Patent Office: 637 Days
• Field of Search: 257329-334, 257/133, 257/146, 257/341, 257/343, 257/E29.027
• US Class Current: 257/334
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.

Claims

1. A transistor device comprising a first vertical transistor structure, wherein the first vertical transistor structure comprises:

a substrate;

a first dielectric layer disposed in a first trench of the substrate;

a first gate disposed in the first dielectric layer, wherein the first gate defines, at both sides thereof, a first channel region and a second channel region in the substrate, wherein the first gate has a cylindrical structure, and the first channel region and the second channel region are respectively a curved channel disposed at both sides of the cylindrical structure;

a first doped region disposed in the substrate, wherein the first doped region is located below the first channel region;

a second doped region disposed in the substrate, wherein the second doped region is located above the first channel region;

a third doped region disposed in the substrate, wherein the third doped region is located below the second channel region; and

a fourth doped region disposed in the substrate, wherein the fourth doped region is located above the second channel region.

2. The transistor device of claim 1, wherein a width of the first gate is greater than a width of the first trench.

3. The transistor device of claim 1, further comprising a second vertical transistor structure, wherein the second vertical transistor structure comprises:

a second dielectric layer disposed in a second trench of the substrate;

a second gate disposed in the second dielectric layer, wherein the second gate defines, at both sides thereof, a third channel region and a fourth channel region in the substrate;

the third doped region, disposed below the third channel region and shared by the first vertical transistor structure and the second vertical transistor structure;

a fifth doped region disposed in the substrate, wherein the fifth doped region is located above the third channel region;

a sixth doped region disposed in the substrate, wherein the sixth doped region is located below the fourth channel region; and

a seventh doped region disposed in the substrate, wherein the seventh doped region is located above the fourth channel region.

4. The transistor device of claim 3, wherein a width of the second gate is greater than a width of the second trench.

5. The transistor device of claim 4, wherein the second gate is cylindrical in shape.

6. The transistor device of claim 3, further comprising:

a third dielectric layer disposed in a third trench of the substrate, wherein the third dielectric layer is located between the first gate and the second gate; and

a bit line disposed at a bottom of the third trench, wherein the bit line is located below the third dielectric layer and between the first dielectric layer and the second dielectric layer.