Lateral connection for a via-less thin film resistor

• US 8,659,085 B2
• Filed: 08/24/2010
• Issued: 02/25/2014
• Est. Priority Date: 08/24/2010
• Status: Active Grant

• Current Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Ng, Hui Chong Vince, Le Neel, Olivier, Leung, Calvin
• Primary Examiner(s): Ingham, John C
• Application Number:
  US12/862,589
• Publication Number:
  US 20120049323A1
• Time in Patent Office: 1,281 Days
• Field of Search: 257/359, 257/E21.006, 257/536, 257/537, 438/384, 438/385
• US Class Current: 257/359
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 2221/1078 Multiple stacked thin films not being formed in openings in dielectrics
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure is directed to an integrated circuit having a substrate and a first and a second interconnect structure over the substrate. Each interconnect structure has a first conductive layer over the substrate and a second conductive layer over the first conductive layer. The integrated circuit also includes a thin film resistor over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

Claims

1. An integrated circuit, comprising:

a substrate;

a first interconnect structure over the substrate, the first interconnect structure electrically connecting a first contact and a second contact spaced from each other on the substrate;

a second interconnect structure over the substrate spaced from the first interconnect structure, the second interconnect structure electrically connecting a third contact and a fourth contact spaced from each other on the substrate, each interconnect structure having a first conductive layer over the substrate and a second conductive layer over the first conductive layer, wherein the first and the second interconnect structures have a protective coating over the second conductive layer; and

a thin film resistor positioned over a portion of the substrate between the first and the second interconnect structures and abutting sidewalls of the first and second conductive layers of the first and second interconnect structures, the thin film resistor electrically connecting the first conductive layers of the first and second interconnect structures to each other, wherein the thin film resistor is over at least a portion of a top surface of the protective coating of the first and the second interconnect structures.

2. The integrated circuit of claim 1 wherein the substrate is an electrical insulator positioned above transistors.

3. The integrated circuit of claim 1, further comprising:

an interlevel dielectric over the first and second interconnect structures, the thin film resistor, and the substrate;

a first contact through the interlevel dielectric and the protective coating to the first interconnect structure; and

a third interconnect structure coupled to the first interconnect structure through the first contact.

4. The integrated circuit of claim 1, further comprising:

an antireflective coating between the second conductive layer and the protective coating of the first and the second interconnect structures.

5. The integrated circuit of claim 1 wherein the protective coating has a different etch chemistry from the thin film resistor.

6. The integrated circuit of claim 1 wherein the thin film resistor is chromium silicon.

7. The integrated circuit of claim 1 wherein the thin film resistor has a thickness in the range of 50 and 200 angstroms.

8. The integrated circuit of claim 1 wherein the second conductive layer has a thickness in the range of 5,000 and 10,000 angstroms.

9. The integrated circuit of claim 1 further comprising a dielectric cap over the thin film resistor.

10. The integrated circuit of claim 1 wherein the thin film resistor is a plurality of resistive layers.

11. The integrated circuit of claim 10 wherein a first resistive layer is over the substrate and a second resistive layer is over the first resistive layer.

12. An integrated circuit, comprising:

a semiconductor substrate;

a first interconnect structure over the semiconductor substrate, the first interconnect structure electrically connecting a first contact region and a second contact region spaced from each other on the semiconductor substrate;

a second interconnect structure over the semiconductor substrate spaced from the first interconnect structure, the second interconnect structure electrically connecting a third contact region and a fourth contact region spaced from each other on the semiconductor substrate, each interconnect structure having a first conductive layer over the semiconductor substrate and a second conductive layer over the first conductive layer, wherein the first and the second interconnect structures have a protective coating over the second conductive layer; and

a thin film resistor positioned over a portion of the semiconductor substrate between the first and the second interconnect structures and abutting sidewalls of the first and second conductive layers of the first and second interconnect structures, the thin film resistor electrically connecting the first conductive layers of the first and second interconnect structures to each other, wherein the thin film resistor is over at least a portion of a top surface of the protective coating of the first and the second interconnect structures.

13. The integrated circuit of claim 12 further comprising a dielectric cap over the thin film resistor.

14. The integrated circuit of claim 12 wherein the thin film resistor is a plurality of resistive layers.

15. An integrated circuit, comprising:

a substrate;

a first interconnect structure over the substrate, the first interconnect structure electrically connecting a first contact and a second contact spaced from each other on the substrate;

a second interconnect structure over the substrate spaced from the first interconnect structure, the second interconnect structure electrically connecting a third contact and a fourth contact spaced from each other on the substrate, each interconnect structure having a first conductive layer over the substrate, a second conductive layer over the first conductive layer, and a protective coating over the second conductive layer; and

a thin film resistor positioned over a portion of the substrate between the first and the second interconnect structures and over at least a portion of a top surface of the protective coating of the first and the second interconnect structures, the thin film resistor electrically connecting the first conductive layers of the first and second interconnect structures to each other.

16. The integrated circuit of claim 15, further comprising:

an interlevel dielectric over the first and second interconnect structures, the thin film resistor, and the substrate;

a first contact through the interlevel dielectric and the protective coating to the first interconnect structure; and

a third interconnect structure coupled to the first interconnect structure through the first contact.

17. The integrated circuit of claim 15, further comprising:

an antireflective coating between the second conductive layer and the protective coating of the first and the second interconnect structures.

18. An integrated circuit, comprising:

a semiconductor substrate;

a first interconnect structure over the semiconductor substrate, the first interconnect structure electrically connecting a first contact region and a second contact region spaced from each other on the semiconductor substrate;

a second interconnect structure over the semiconductor substrate spaced from the first interconnect structure, the second interconnect structure electrically connecting a third contact region and a fourth contact region spaced from each other on the semiconductor substrate, each interconnect structure having a first conductive layer over the semiconductor substrate, a second conductive layer over the first conductive layer, a protective coating over the second conductive layer; and

a thin film resistor positioned over a portion of the semiconductor substrate between the first and the second interconnect structures and over at least a portion of a top surface of the protective coating of the first and the second interconnect structures, the thin film resistor electrically connecting the first conductive layers of the first and second interconnect structures to each other.

19. The integrated circuit of claim 18 further comprising a dielectric cap over the thin film resistor.

20. The integrated circuit of claim 18 wherein the thin film resistor is a plurality of resistive layers.