Lateral power diode with self-biasing electrode

• US 8,659,117 B2
• Filed: 02/03/2012
• Issued: 02/25/2014
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Diaz, Jose R
• Application Number:
  US13/365,983
• Publication Number:
  US 20120133016A1
• Time in Patent Office: 753 Days
• Field of Search: 257/520, 257/341, 257/335, 257/E29.261, 438/335, 438/360, 438/361, 438/430, 438/454, 438/35
• US Class Current: 257/520
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Claims

1. A Schottky diode comprising:

a drift region of a first conductivity type;

a lightly doped silicon region of the first conductivity type disposed in the drift region;

a conductor layer disposed on and in contact with the lightly doped silicon region, the conductor layer forming a Schottky contact with the lightly doped silicon region;

a highly doped silicon region of the first conductivity type disposed in the drift region, the highly doped silicon region being spaced from the lightly doped silicon region in the drift region such that upon biasing the Schottky diode in a conducting state, a current flows between the lightly doped silicon region and the highly doped silicon region through the drift region; and

a trench extending into the drift region perpendicular to a direction of the current flow, the trench including a dielectric layer disposed on at least a portion of a sidewall of the trench and at least one conductive electrode disposed within the dielectric layer.

2. The Schottky diode of claim 1, wherein the conductive electrode electrically contacts the drift region along an upper portion of the sidewall of the trench.

3. The Schottky diode of claim 1, wherein the drift region is disposed on a silicon region of the first conductivity type, the silicon region having a higher doping concentration than the drift region.

4. The Schottky diode of claim 1, wherein the conductive electrode electrically contacts the drift region along a bottom surface of the trench.

5. The Schottky diode of claim 1, wherein the drift region is disposed over a silicon region, the silicon region having a lower doping concentration than a doping concentration of the drift region, the trench extending through the drift region and terminating within the silicon region, the conductive electrode electrically contacting the silicon region along a bottom surface of the trench.

6. The Schottky diode of claim 5, wherein the silicon region is disposed on a buried dielectric layer.

7. The Schottky diode of claim 1, wherein the drift region is disposed on a buried dielectric layer.

8. The Schottky diode of claim 1, wherein the conductive electrode is of a second conductivity type.

9. The Schottky diode of claim 1, further comprising at least one additional trench extending into the drift region perpendicular to the direction of the current flow, the at least one additional trench including a second dielectric layer disposed on at least a portion of a sidewall of the at least one additional trench and a second conductive electrode disposed within the second dielectric layer, the trench and the at least one additional trench being located between the lightly doped silicon region and the highly doped silicon region in a staggered configuration.

10. The Schottky diode of claim 1, further comprising a conductive plug extending into the highly doped silicon region.

11. The Schottky diode of claim 10, wherein the conductive plug and the trench extend to substantially a same depth.

12. A method of forming a Schottky diode, comprising:

forming a lightly doped silicon region of a first conductivity type in a drift region of the first conductivity type;

forming a conductor layer on and in contact with the lightly doped silicon region, the conductor layer forming a Schottky contact with the lightly doped silicon region;

forming a highly doped silicon region of the first conductivity type in the drift region, the highly doped silicon region being spaced from the lightly doped silicon region such that upon biasing the Schottky diode in a conducting state, a current flows between the lightly doped silicon region and the highly doped silicon region through the drift region;

forming a trench extending into the drift region perpendicular to a direction of the current flow;

forming a dielectric layer lining at least a portion of sidewall of the trench; and

forming a conductive electrode in the trench.

13. The method of claim 12, wherein the dielectric layer is formed such that the conductive electrode electrically contacts the drift region along an upper portion of the sidewall of the trench.

14. The method of claim 12, further comprising forming an epitaxial layer disposed on a substrate of the first conductivity type, the epitaxial layer including the drift region, the substrate having a higher doping concentration than the drift region.

15. The method of claim 12, wherein the dielectric layer is formed such that the conductive electrode electrically contacts the drift region along a bottom surface of the trench.

16. The method of claim 12, wherein the forming the conductive electrode includes forming a polysilicon layer disposed in the trench, the polysilicon layer including an in-situ doped polysilicon layer of a second conductivity type.

17. A semiconductor diode comprising:

a semiconductor region of a first conductivity type;

an anode region of a second conductivity type, the anode region being disposed within the semiconductor region, the anode region and the semiconductor region forming a pn junction therebetween;

doped silicon region of the first conductivity type, the doped silicon region being disposed in the semiconductor region, the doped silicon region being spaced from the anode region such that upon biasing the semiconductor diode in a conducting state, a current flows between the anode region and the doped silicon region through the semiconductor region; and

a trench extending into the semiconductor region perpendicular to a direction of the current flow, the trench including;

a dielectric layer lining disposed on at least a portion of a sidewall of the trench; and

a conductive electrode, the conductive electrode being in electrical contact and in direct physical contact with the semiconductor region along a bottom surface of the trench.

18. The semiconductor diode of claim 17, wherein the doped silicon region of the first conductivity type is a first doped silicon region of the first conductivity type, the semiconductor region including a drift region of the first conductivity type disposed on a second doped silicon region of the first conductivity type, the second doped silicon region having a higher doping concentration than the drift region.

19. The semiconductor diode of claim 17, wherein the doped silicon region of the first conductivity type is a first doped silicon region of the first conductivity type, the semiconductor region including a drift region of the first conductivity type disposed on a second doped silicon region of the first conductivity type, the second silicon doped region having a lower doping concentration than the drift region, the trench extending through the drift region and terminating within the second doped silicon region, the conductive electrode being in electrical contact and direct physical contact with the second doped silicon region along the bottom surface of the trench.

20. The semiconductor diode of claim 19, wherein the second doped silicon region is disposed on a second dielectric layer.

21. The semiconductor diode of claim 17, wherein the semiconductor region is disposed on a second dielectric layer.

22. The semiconductor diode of claim 17, wherein the conductive electrode is of the second conductivity type.

23. The semiconductor diode of claim 17, further comprising at least one additional trench extending into the semiconductor region perpendicular to the direction of the current flow, the at least one additional trench including a second dielectric layer disposed on at least a portion of a sidewall of the at least one additional trench and a second conductive electrode disposed within the second dielectric layer, the trench and the at least one additional trench being located between the anode region and the doped silicon region in a staggered arrangement.

24. The semiconductor diode of claim 17, further comprising a conductive plug extending into the doped silicon region.

25. The semiconductor diode of claim 24, wherein the conductive plug and the trench extend to substantially a same depth.

26. A method of forming a semiconductor diode comprising:

forming an anode region in a semiconductor region of a first conductivity type, the anode region being of a second conductivity type, the anode region and the semiconductor region forming a pn junction therebetween;

forming a highly doped silicon region of the first conductivity type in the semiconductor region, the highly doped silicon region being spaced from the anode region such that upon biasing the semiconductor diode in a conducting state, a current flows between the anode region and the highly doped silicon region through the semiconductor region;

forming a trench extending into the semiconductor region perpendicular to a direction of the current flow;

forming a dielectric layer lining at least a portion of a sidewall of the trench; and

forming a conductive electrode in the trench, wherein the dielectric layer is formed such that the conductive electrode is in electrical contact and in direct physical contact with the semiconductor region along a bottom surface of the trench.

27. The method of claim 26, further comprising forming the semiconductor region of the first conductivity type on a substrate of the first conductivity type, the substrate having a higher doping concentration than the semiconductor region.

28. The method of claim 26, wherein the forming the conductive electrode includes forming a polysilicon layer disposed within the trench, the polysilicon layer including an in-situ doped polysilicon layer having the second conductivity type.

29. The method of claim 26, further comprising forming the semiconductor region of the first conductivity type on a substrate of the first conductivity type, the substrate having a lower doping concentration than the semiconductor region.