Integrated circuit ground shielding structure

• US 8,659,126 B2
• Filed: 12/07/2011
• Issued: 02/25/2014
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Ling, Yen, Hsiao-Tsung, Chen, Ho-Hsiang, Jou, Chewn-Pu
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/313,240
• Publication Number:
  US 20130147023A1
• Time in Patent Office: 811 Days
• Field of Search: 257/531, 257/659, 257/621, 257/E27.011, 257/E23.114, 361/816, 361/799, 361/800, 361/818, 361/821
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

Claims

1. An apparatus, comprising:

a first die that contains an electronic component;

second die that contains a ground shielding structure, wherein the ground shielding structure device includes a first segment and a second segment, and wherein the first and second segments are formed in different layers, wherein the first and second segments each have a meandrous shape, and wherein the first and second segments are positionally offset from one another in a top view; and

a layer disposed between the first die and the second die, wherein the layer couples the first die and the second die together.

2. The apparatus of claim 1, wherein:

the electronic component and the ground shielding structure each contain a conductive material; and

the electronic component is an inductor coil.

3. The apparatus of claim 1, wherein the first die and the second die each include a silicon substrate or an interposer substrate.

4. The apparatus of claim 1, wherein the layer includes an underfill material.

5. The apparatus of claim 1, wherein the layer has a thickness that is at least ten microns.

6. The apparatus of claim 1, wherein the layer contains one or more microbumps.

7. The apparatus of claim 1, wherein at least one of the first and second dies contains one or more dummy metal devices.

8. The apparatus of claim 3, wherein the interposer substrate includes a dielectric material, a high resistance material, or a glass material.

9. A device, comprising:

an inductor coil formed in a first die;

a patterned ground shielding (PGS) device formed in a second die separate from the first die, wherein the PGS device contains a first elongate winding portion and a second elongate winding portion; and

an underfill material located between the first die and the second die.

10. The device of claim 9, wherein one of the first and second dies includes a silicon substrate, and the other one of the first and second dies includes an interposer substrate.

11. The device of claim 9, wherein one of the first and second dies includes at least one dummy metal.

12. The device of claim 9, wherein the underfill material includes at least one dummy microbump.

13. The device of claim 9, wherein the first elongate winding portion and the second elongate winding portion are formed in two separate metal layers, the first elongate winding portion and the second elongate winding portion being misaligned with respect to each other in a top view.

14. The device of claim 10, wherein:

the silicon substrate includes a plurality of microelectronic devices formed therein; and

the interposer substrate includes one of;

a dielectric material and a glass material.

15. The device of claim 12, wherein the dummy microbump is surrounded by the inductor coil in a top view.

16. A microelectronic device, comprising:

a first die that contains a plurality of first interconnect layers, wherein an inductor coil structure is disposed in a subset of the first interconnect layers;

a second die that contains a plurality of second interconnect layers, wherein a patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers; and

an underfill layer disposed between the first and second dies, the underfill layer containing one or more microbumps.

17. The microelectronic device of claim 16, wherein the first die and the second die each include a substrate that is one of:

a silicon substrate and an interposer substrate.

18. The microelectronic device of claim 16, wherein:

at least one of the first and second dies contains a plurality of dummy metal components; and

the underfill layer contains a plurality of dummy microbumps that are surrounded by the inductor coil structure in a top view.

19. The microelectronic device of claim 16, wherein the PGS structure includes a first segment and a second segment that are formed in different layers of the second interconnect layers, and wherein the first and second segments each have a meandering shape and are misaligned with each other in a top view.