Semiconductor device having an interconnect structure with TSV using encapsulant for structural support

• US 8,659,162 B2
• Filed: 09/26/2011
• Issued: 02/25/2014
• Est. Priority Date: 06/08/2009
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Suthiwongsunthorn, Nathapong, Marimuthu, Pandi C., Ku, Jae Hun, Omandam, Glenn, Goh, Hin Hwa, Heng, Kock Liang, Caparas, Jose A.
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/245,099
• Publication Number:
  US 20120013004A1
• Time in Patent Office: 883 Days
• Field of Search: 257/774, 257/396, 257/734, 257/622, 257/678, 257/701, 257/736, 257/737, 257/787, 257/781, 257/E21.006, 257/E21.051, 257/E21.17, 257/E21.352, 257/E21.499, 257/E21.502, 257/E21.508
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a via extending through the substrate;

a first insulating layer disposed on sidewalls of the via;

an electrically conductive material disposed in the via over the first insulating layer to form a through silicon via (TSV);

a first interconnect structure disposed over a first surface of the substrate;

a semiconductor die or component mounted to the first interconnect structure;

an encapsulant disposed over the first interconnect structure and semiconductor die or component; and

a second interconnect structure disposed over a second surface of the substrate, the second interconnect structure being electrically connected to the TSV.

2. The semiconductor device of claim 1, wherein the first interconnect structure includes:

a first conductive layer disposed over the TSV;

a second insulating layer disposed over the first conductive layer and substrate;

a second conductive layer disposed over the first conductive layer; and

a third insulating layer disposed over the second conductive layer and second insulating layer.

3. The semiconductor device of claim 2, wherein the first interconnect structure further includes:

a conductive pillar disposed over the second conductive layer;

a fourth insulating layer disposed around the conductive pillar; and

a third conductive layer disposed over the conductive pillar, wherein the third conductive layer is electrically connected to the semiconductor die or component.

4. The semiconductor device of claim 1, further including a printed circuit board, the semiconductor device mounted to the printed circuit board through the second interconnect structure.

5. The semiconductor device of claim 1, wherein the second interconnect structure includes:

a second insulating layer disposed over the second surface of the substrate and TSV; and

a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

6. The semiconductor device of claim 1, wherein the second interconnect structure includes:

a second insulating layer disposed over the second surface of the substrate and the TSV;

a first conductive layer disposed over the TSV to extend the conductivity of the TSV;

a third insulating layer disposed over the second insulating layer and the first conductive layer; and

a second conductive layer disposed over the first conductive layer.

7. A semiconductor device, comprising:

a substrate;

a conductive via disposed through the substrate;

a first interconnect structure disposed over a first surface of the substrate;

a semiconductor die or component disposed over the first interconnect structure and the conductive via;

an encapsulant deposited over the first interconnect structure and semiconductor die or component; and

a second interconnect structure disposed over a second surface of the substrate and electrically connected to the conductive via.

8. The semiconductor device of claim 7, wherein the first interconnect structure includes:

a first conductive layer disposed over the conductive via;

a first insulating layer disposed over the first conductive layer and substrate;

a second conductive layer disposed over the first conductive layer;

a second insulating layer disposed over the second conductive layer and first insulating layer;

a conductive pillar disposed over the second conductive layer;

a third insulating layer disposed around the conductive pillar; and

a third conductive layer disposed over the conductive pillar and electrically connected to the semiconductor die or component.

9. The semiconductor device of claim 7, wherein the first interconnect structure includes a conductive bump.

10. The semiconductor device of claim 7, the second interconnect structure including:

a first insulating layer disposed over the second surface of the substrate and the conductive via; and

a first conductive layer disposed over the conductive via.

11. The semiconductor device of claim 7, wherein the second interconnect structure includes:

a first insulating layer disposed over the substrate;

a first conductive layer disposed over the conductive via to extend the conductivity of the conductive via;

a second insulating layer disposed over the first insulating layer and first conductive layer; and

a second conductive layer disposed over the first conductive layer.

12. The semiconductor device of claim 7, wherein a thickness of the substrate is less than 300 μ

m.

13. A semiconductor device, comprising:

a substrate;

a conductive via disposed through the substrate;

a first interconnect structure disposed over a first surface of the substrate;

a semiconductor die or component disposed over the first interconnect structure; and

an encapsulant disposed over the first interconnect structure and the semiconductor die or component.

14. The semiconductor device of claim 13, further including a second interconnect structure disposed over a second surface of the substrate, the second interconnect structure electrically connected to the conductive via.

15. The semiconductor device of claim 13, wherein the first interconnect structure includes a bond wire.

16. The semiconductor device of claim 14, wherein the second interconnect structure includes:

a first insulating layer disposed over the second surface of the substrate; and

a first conductive layer disposed over the conductive via.

17. The semiconductor device of claim 14, wherein the second interconnect structure includes:

a first insulating layer disposed over the second surface of the substrate;

a first conductive layer disposed over the conductive via to extend the conductivity of the conductive via;

a second insulating layer disposed over the first insulating layer and the first conductive layer; and

a second conductive layer disposed over the first conductive layer.

18. The semiconductor device of claim 13, wherein the first interconnect structure includes:

a first conductive layer disposed over the conductive via;

a first insulating layer disposed over the first conductive layer and the substrate;

a second conductive layer disposed over the first insulating layer;

a second insulating layer disposed over the second conductive layer and the first insulating layer;

a conductive pillar disposed over the second conductive layer;

a third insulating layer disposed around the conductive pillar; and

a third conductive layer disposed over the conductive pillar, the semiconductor die or component electrically connected to the third conductive layer.

19. The semiconductor device of claim 13, wherein a thickness of the substrate is in a range of about 10 μ

m to about 50 μ

m.

20. A semiconductor device, comprising:

a substrate;

a conductive via disposed partially through the substrate;

a first interconnect structure disposed over a first surface of the substrate;

a semiconductor component disposed over the first interconnect structure; and

an encapsulant disposed over the first interconnect structure and the semiconductor component.

21. The semiconductor device of claim 20, wherein the first interconnect structure includes a conductive paste.

22. The semiconductor device of claim 20, wherein the first interconnect structure includes:

a first conductive layer over the conductive via;

a first insulating layer over the first conductive layer;

a second conductive layer over the first insulating layer; and

a second insulating layer over the second conductive layer and the first insulating layer.

23. The semiconductor device of claim 22, wherein the first interconnect structure further includes:

a conductive pillar over the second conductive layer;

a third insulating layer around the conductive pillar; and

a third conductive layer over the conductive pillar, the semiconductor component electrically connected to the third conductive layer.

24. The semiconductor device of claim 20, wherein a thickness of the substrate is in a range of 10 μ

m to 50 μ

m.

25. The semiconductor device of claim 20, wherein a thickness of the substrate is less than 300 μ

m.