Calibration for mixed-signal integrator architecture

• US 8,659,343 B2
• Filed: 02/24/2012
• Issued: 02/25/2014
• Est. Priority Date: 02/25/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Erdogan, Ozan E., Shen, Guozhong, Anantharaman, Rajesh, Taparia, Ajay, Javid, Behrooz, Mahmud, Syed T.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US13/404,817
• Publication Number:
  US 20120218020A1
• Time in Patent Office: 732 Days
• Field of Search: 327/336, 327/337, 327/339, 327/341, 327/345
• US Class Current: 327/336
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

Claims

1. An integration circuit comprising:

a. an input control switch configured to switch to a first position coupled to an input voltage signal and to a second position coupled to ground;

b. an integrator coupled to an output of the input control switch, wherein the integrator is configured to output an integrated output voltage,

wherein the integrator comprises;

a resistive element coupled to the output of the input control switch;

an amplifier coupled to an output of the resistive element; and

an integrating feedback capacitor coupled to an input of the amplifier and to an output of the amplifier;

c. a voltage adjustment circuit coupled to the integrator and comprising a charge dump capacitor, wherein the voltage adjustment circuit is configured to adjust the integrated output voltage by a voltage adjustment,

wherein the value of the voltage adjustment is set by a capacitance ratio of the charge dump capacitor and the integrating feedback capacitor; and

d. a logic circuit coupled to the voltage adjustment circuit and to the input control switch, wherein the logic circuit is configured to control the voltage adjustment circuit and the input control switch, further wherein when the input control switch is set to the first position the integrator integrates the input voltage signal and the voltage adjustment circuit adjusts the integrated output voltage by the voltage adjustment if the integrated output voltage reaches one or more defined limits, and when the input control switch is set to the second position the integrator, the voltage adjustment circuit, and the logic circuit are configured to perform a calibration process that measures a value of the adjustment value.

2. The integration circuit of claim 1 wherein the voltage adjustment circuit further comprises a plurality of switches, wherein the charge dump capacitor is coupled to the integrating feedback capacitor via a first switch of the plurality of switches, and the plurality of switches are coupled to the logic circuit.

3. The integration circuit of claim 1 further comprising an analog-to-digital converter coupled to the output of the integrator to convert the integrated output voltage to a digital value at each integration time period.

4. The integration circuit of claim 3 wherein the logic circuit is configured to perform the calibration process by measuring the digital value output from the analog-to-digital converter while the input control switch is in the second position, forcing the voltage adjustment circuit to adjust the integrated output voltage by the voltage adjustment while the input control switch is in the second position, and measuring the digital value output from the analog-to-digital converter after the forced voltage adjustment while the switch is in the second position.

5. The integration circuit of claim 1 wherein the voltage adjustment value is a fixed value Vj.

6. The integration circuit of claim 1 further comprising a comparison circuit coupled to the integrator, wherein the comparison circuit is configured to receive the integrated output voltage, to compare the integrated output voltage to the one or more defined limits, and to output a comparison result to the logic circuit.

7. The integration circuit of claim 1 wherein the logic circuit includes program instructions configured to perform the steps of comparing the integrated output voltage to the one or more defined limits, and to control the voltage adjustment circuit according to a comparison result.

8. The integration circuit of claim 1 wherein the resistive element has a fixed impedance.

9. The integration circuit of claim 1 wherein the resistive element has a time-varying impedance.

10. A method of calibrating an integration circuit, the method comprising:

a. coupling an input of an integrator to ground, the integrator comprising;

a resistive element;

an amplifier coupled to an output of the resistive element; and

an integrating feedback capacitor coupled to an input of the amplifier and to an output of the amplifier;

b. discharging the integrating feedback capacitor within the integrator, wherein an output of the integrating feedback capacitor outputs an integrated output voltage according to a current charge accumulated by the integrating feedback capacitor;

c. measuring the integrated output voltage to determine a first calibration voltage;

d. applying a charge dump to the integrating feedback capacitor thereby adjusting the integrated output voltage by a voltage adjustment set based on a capacitance ratio of the integrating feedback capacitor and a charge dump capacitor;

e. measuring the integrated output voltage after application of the charge dump to determine a second calibration voltage;

f. calculating a difference between the first calibration voltage and the second calibration voltage to determine a measured adjustment voltage value that corresponds to the charge dump; and

g. discharging the integrating feedback capacitor.

11. The method of claim 10 wherein calculating the difference between the first calibration voltage and the second calibration voltage comprises converting the first calibration voltage to a first digital value, converting the second calibration voltage to a second digital value, and calculating a difference between the first digital value and the second digital value.

12. The method of claim 10 further comprising:

a. coupling the input of the integrator to receive an input voltage signal;

b. comparing the integrated output voltage to one or more threshold values to determine if the integrated output voltage is within a voltage range;

c. adjusting the charge on the integrating feedback capacitor by applying the charge dump if the integrated output voltage is not within the voltage range, thereby maintaining the integrated output voltage within the voltage range;

d. determining an accumulated voltage change corresponding to a number of adjustments in charge applied within an integrating period multiplied by the measured adjustment voltage value; and

e. determining a total integration voltage over the integrating period by adding the accumulated voltage change to the integrated output voltage at the end of the integrating period.

13. The method of claim 12 wherein adjusting the charge comprises decreasing the charge on the integrating feedback capacitor if the integrated output voltage is greater than or equal to a high threshold value, and increasing the charge on the integrating feedback capacitor if the integrated output voltage is less than or equal to a low threshold voltage, wherein decreasing the charge on the integrating feedback capacitor decreases the integrated output voltage and increasing the charge on the integrating feedback capacitor increases the integrated output voltage.

14. The method of claim 12 wherein comparing the integrated output voltage to one or more threshold values is performed in software.

15. The method of claim 12 wherein comparing the integrated output voltage to one or more threshold values is performed using one or more comparators.

16. The method of claim 12 wherein adjusting the charge on the integrating feedback capacitor results in adjusting the integrated output voltage.

17. The method of claim 12 wherein determining the total integration voltage comprises converting the integrated output voltage to a digital value at each integration time period and adding the accumulated voltage change to the digital value.

18. The method of claim 10 wherein the measured adjustment voltage value comprises a fixed value.