Voltage programmed pixel circuit, display system and driving method thereof

• US 8,659,518 B2
• Filed: 07/03/2013
• Issued: 02/25/2014
• Est. Priority Date: 01/28/2005
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, Gholamreza, Servati, Peyman
• Primary Examiner(s): Lao, Lun-Yi
• Assistant Examiner(s): ABDIN, SHAHEDA A
• Application Number:
  US13/934,652
• Publication Number:
  US 20130293522A1
• Time in Patent Office: 237 Days
• Field of Search: 345 76- 82, 345/204, 345/214, 315/169.3, 313/463
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A voltage programmed pixel circuit, display system having the pixel circuit and driving method thereof is provided. The pixel circuit includes a light emitting device, a driving transistor connected to the light emitting device and a programming circuit. The programming circuit adjusts a pixel current during a programming cycle of the pixel circuit.

Claims

1. A method of driving a pixel circuit, the pixel circuit comprising a light emitting device having a first electrode and a second electrode;

a driving transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the driving transistor being connected to the first electrode of the light emitting device;

a first capacitor having first and second terminals, the first terminal of the first capacitor being connected to the gate terminal of the driving transistor, the second terminal of the first capacitor being connected to the first terminal of the driving transistor and the first electrode of the light emitting device;

a first switch transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the first switch transistor being connected the gate terminal of the driving transistor and the first terminal of the first capacitor; and

a programming circuit having a programming transistor, the programming transistor being connected to the first electrode of the light emitting device and having a gate terminal directly connected to a data line;

the method comprising the steps of;

at a programming cycle of the pixel circuit, turning the programming transistor on;

after the programming cycle, turning the programming transistor off for the remainder of a frame time comprising the programming cycle followed by a driving cycle during the frame time.

2. The method of claim 1, wherein during the driving cycle, a voltage at a second node between the first electrode of the light emitting device and a first terminal of the driving transistor goes to a voltage across the light emitting device.

3. The method of claim 2, wherein during the driving cycle, a voltage at a first node defined between the first terminal of the first switch transistor, the gate terminal of the driving transistor, and the first terminal of the first capacitor goes to a voltage that is a function of an aspect ratio of the driving transistor, an aspect ratio of the programming transistor, a programming voltage applied during the programming cycle, the voltage across the light emitting device at the second node, and a shift in a threshold voltage of the driving transistor.

4. The method of claim 1, wherein during the driving cycle following the programming cycle, any shift in a threshold voltage of the programming transistor that occurred during the programming cycle is negligible.

5. The method of claim 1, wherein the programming transistor is on for a small fraction of time during the programming cycle relative to the frame time such that any shift in a threshold voltage of the programming transistor is negligible.

6. The method of claim 1, wherein a first terminal of the programming transistor is connected to the second terminal of the first capacitor and to the first electrode of the light emitting device, and a second terminal of the programming transistor is connected to a controllable voltage line that controls a biasing condition of the programming transistor.

7. The method of claim 6, wherein a negative voltage is applied to the second terminal of the programming transistor during the programming cycle.

8. The method of claim 1, wherein the light emitting device includes an organic light emitting diode (OLED), and the first switch, driving, and programming transistors are n-type and/or p-type thin-film transistors.

9. The method of claim 1, wherein the programming circuit includes a second switch transistor and a second capacitor, the second switch transistor having a gate terminal, a first terminal and a second terminal, the second capacitor having a first terminal and a second terminal, the gate terminal of the programming transistor being connected to the first terminal of the second switch transistor and the first terminal of the second capacitor.

10. The method of claim 1, wherein, during the programming cycle of an nth row, a predetermined voltage is provided to the second terminal of the programming transistor while, during the programming cycle of the (n+1)th row, an address signal of an (n+1)th row is provided to a first switch transistor of a pixel circuit in the (n+1)th row.

11. The method of claim 1, wherein the light emitting device is an OLED, and wherein the programming transistor is under stress for a small fraction of the frame time and adjusting the pixel current, while the driving transistor drives the OLED.

12. The method of claim 1, wherein the programming transistor is a TFT, and the pixel circuit incorporates a short-term biasing condition in which the programming TFT is stable.