Protective circuit board cover

• US 8,659,908 B2
• Filed: 10/14/2010
• Issued: 02/25/2014
• Est. Priority Date: 10/14/2009
• Status: Active Grant

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Adams, Christian, Kelley, Matthew, Nelson, Patrick
• Primary Examiner(s): Semenenko, Yuriy
• Application Number:
  US12/904,872
• Publication Number:
  US 20110090658A1
• Time in Patent Office: 1,230 Days
• Field of Search: 361760-765, 361/792, 361/818, 174/250, 174/258, 174/520, 174260-262, 257788-790
• US Class Current: 361/765
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/49227 Insulator making

Abstract

A protective, anti-tamper coating and methods of coating creation and application are provided. The coating may include an elastomeric layer to allow for strippability/removal. The coating may also include a “smart layer” for tamper detection, imaging prevention, and tamper prevention or underlying device de-activation/alteration upon tamper detection. The coating may also include one or more ground planes around the smart layer and one or more frangible layers designed to interrupt or alter smart layer function in the event of a tamper attempt.

Claims

1. An anti-tamper coating for a component, the coating comprising:

a foundation layer that includes a thermal via and a component connection via, the foundation layer being disposed on the component;

a smart layer disposed on top of the foundation layer, the smart layer including an active circuit component operably connected to the component through the component connection via;

a capping layer disposed on top of the smart layer and equipped with a frangible portion such that a tamper attempt breaks the frangible portion, thereby causing physical damage to the active circuit component;

where the active circuit component in the smart layer includes at least one of a logic device and a memory device.

2. The coating of claim 1, where the foundation layer includes an elastomeric undercoat and where the elastomeric undercoat includes at least one of a thermal via and a component connection via.

3. The coating of claim 1, where the smart layer includes at least two sub-layers, each sub-layer including at least one active circuit component operably connected to at least one of the active circuit component or a signal pathway in the other sub-layer.

4. The coating of claim 1, where the foundation layer includes a frangible portion such that breakage of the frangible portion causes disruptive or destructive interactions between the active circuit component and the coated component.

5. The coating of claim 1, further including a ground plane layer disposed between the foundation layer and the smart layer.

6. The coating of claim 1, wherein the capping layer includes an electromagnetic shielding portion.

7. The coating of claim 1, further including a ground plane disposed between the smart layer and the capping layer.

8. The coating of claim 1, the coating further comprising a first ground plane disposed between the smart layer and the foundation layer and a second ground plane disposed on top of the smart layer.

9. The coating of claim 8, the coating further comprising a second smart layer disposed between the second ground plane and the capping layer.

10. The coating of claim 1, where the capping layer includes a frangible portion, the frangible portion including damage-causing elements such that breaking the frangible portion causes the damage-causing elements to physically interact with the smart layer.

11. The coating of claim 5, where the foundation layer includes an elastomeric undercoat and where the elastomeric undercoat includes at least one of a thermal via and a component connection via.

12. The coating of claim 5, where the smart layer includes at least two sub-layers, each sub-layer including at least one active circuit component operably connected to at least one of the active circuit component or a signal pathway in the other sub-layer.

13. The coating of claim 5, where the foundation layer includes a frangible portion such that breakage of the frangible portion causes disruptive or destructive interactions between the active circuit component and the coated component.

14. The coating of claim 5, where the capping layer includes a frangible portion, the frangible portion including damage-causing elements such that breaking the frangible portion causes the damage-causing elements to physically interact with the smart layer.

15. The coating of claim 5, wherein the capping layer includes an electromagnetic shielding portion.

16. The coating of claim 5, further including a ground plane disposed between the smart layer and the capping layer.

17. The coating of claim 5, where the active circuit component includes at least one of a logic device and a memory device.

18. The coating of claim 5, the coating further comprising a second ground plane disposed on top of the smart layer.

19. The coating of claim 18, the coating further comprising a second smart layer disposed between the second ground plane and the capping layer.

20. The coating of claim 5, where the ground plane includes damage-causing elements contained in the ground plane and configured such that a tamper event causes the damage-causing elements to physically interact with the smart layer.