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Single device driver circuit to control three-dimensional memory element array

  • US 8,659,932 B2
  • Filed: 09/10/2012
  • Issued: 02/25/2014
  • Est. Priority Date: 08/20/2010
  • Status: Active Grant
First Claim
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1. A memory array, comprising:

  • an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and

    a circuit comprising;

    a bleeder diode having a first terminal coupled to a first word line of the plurality of word lines;

    a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead; and

    at least one first transistor of a first conductivity type having a gate coupled to the word line decoder control lead, at least one of a source or a drain coupled to a word line bias generator circuit, and the other one of the source or the drain coupled to the first word line.

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