Single device driver circuit to control three-dimensional memory element array
First Claim
1. A memory array, comprising:
- an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and
a circuit comprising;
a bleeder diode having a first terminal coupled to a first word line of the plurality of word lines;
a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead; and
at least one first transistor of a first conductivity type having a gate coupled to the word line decoder control lead, at least one of a source or a drain coupled to a word line bias generator circuit, and the other one of the source or the drain coupled to the first word line.
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Accused Products
Abstract
A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.
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Citations
10 Claims
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1. A memory array, comprising:
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an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and a circuit comprising; a bleeder diode having a first terminal coupled to a first word line of the plurality of word lines; a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead; and at least one first transistor of a first conductivity type having a gate coupled to the word line decoder control lead, at least one of a source or a drain coupled to a word line bias generator circuit, and the other one of the source or the drain coupled to the first word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification