Semiconductor memory device with transistor having oxide semiconductor channel formation region

• US 8,659,935 B2
• Filed: 01/25/2013
• Issued: 02/25/2014
• Est. Priority Date: 11/06/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US13/749,961
• Publication Number:
  US 20130140558A1
• Time in Patent Office: 396 Days
• Field of Search: 365/149, 365/72, 365/63, 365/145
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Claims

1. A semiconductor device comprising:

a first line;

a second line;

a third line;

a first memory cell and a second memory cell connected in series between the first line and the second line;

a first circuit configured to select and output any of a plurality of writing potentials to the third line; and

a second circuit configured to compare a potential of the second line with a plurality of reference potentials to read data out,

wherein each of the first memory cell and the second memory cell comprises;

a first transistor including a first gate, a first source, and a first drain;

a second transistor including a second gate, a second source, and a second drain; and

a third transistor including a third gate, a third source, and a third drain,

wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and

wherein the first gate and one of the second source and the second drain are electrically connected to each other,

wherein the first line, the first source, and the third source are electrically connected to one another,

wherein the second line, the first drain, and the third drain are electrically connected to one another, and

wherein the third line and the other of the second source and the second drain are electrically connected to each other.

2. The semiconductor device according to claim 1, further comprising a third circuit configured to generate the plurality of writing potentials and the plurality of reference potentials and supply the plurality of writing potentials and the plurality of reference potentials to the first circuit and the second circuit.

3. The semiconductor device according to claim 1,

wherein each of the first memory cell and the second memory cell further comprises a capacitor, and

wherein the capacitor is electrically connected to the first gate and the one of the second source and the second drain.

4. The semiconductor device according to claim 1, further comprising a fourth circuit supplied with an address signal,

wherein the fourth circuit is electrically connected to the second gate and the third gate.

5. The semiconductor device according to claim 1 further comprising:

a fourth line;

a fifth line;

a fourth transistor including a fourth gate; and

a fifth transistor including a fifth gate,

wherein the fourth gate is electrically connected to the fourth line,

wherein the fifth gate is electrically connected to the fifth line,

wherein the first line is electrically connected to the first source and the third source through the fifth transistor, and

wherein the second line is electrically connected to the first drain and the third drain through the fourth transistor.

6. The semiconductor device according to claim 1, wherein each of the first transistor and the third transistor includes a channel formation region comprising a semiconductor material other than the oxide semiconductor.

7. The semiconductor device according to claim 1, wherein each of the first transistor and the third transistor includes a channel formation region comprising silicon.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor contains In, Ga and Zn.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor contains a crystal of In₂Ga₂ZnO₇.

10. The semiconductor device according to claim 1, wherein hydrogen concentration of the oxide semiconductor is less than or equal to 5×

10¹⁹ atoms/cm³.

11. The semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>—

13</sup> A.

12. A semiconductor device comprising:

a first line;

a second line;

a third line;

a first memory cell and a second memory cell connected in series between the first line and the second line;

a first circuit configured to select and output any of a plurality of writing potentials to the third line;

a second circuit configured to detect conductance between the first line and the second line to read data out; and

a third circuit configured to be supplied with a plurality of reference potentials and select and output any of the plurality of reference potentials,

wherein each of the first memory cell and the second memory cell comprises;

a first transistor having a first gate, a first source, and a first drain;

a second transistor having a second gate, a second source, and a second drain; and

a capacitor comprising a pair of electrodes,

wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and

wherein the first gate, one of the second source and the second drain, and one of the pair of electrodes of the capacitor are electrically connected to one another,

wherein the first line and the first source are electrically connected to each other,

wherein the second line and the first drain are electrically connected to each other,

wherein the third line and the other of the second source and the second drain are electrically connected to each other, and

wherein each of the second gate and the other of the pair of electrodes of the capacitor is electrically connected to the third circuit.

13. The semiconductor device according to claim 12, further comprising a fourth circuit configured to generate the plurality of writing potentials and the plurality of reference potentials and supply the plurality of writing potentials and the plurality of reference potentials to the first circuit, the second circuit and the third circuit.

14. The semiconductor device according to claim 12, further comprising:

a fourth line;

a fifth line;

a third transistor including a third gate; and

a fourth transistor including a fourth gate,

wherein the third gate is electrically connected to the fourth line,

wherein the fourth gate is electrically connected to the fifth line,

wherein the first line is electrically connected to the first source through the fourth transistor, and

wherein the second line is electrically connected to the first drain through the third transistor.

15. The semiconductor device according to claim 12, wherein the first transistor includes a channel formation region comprising a single crystal semiconductor material.

16. The semiconductor device according to claim 12, wherein the first transistor includes a channel formation region comprising silicon.

17. The semiconductor device according to claim 12, wherein the oxide semiconductor contains In, Ga and Zn.

18. The semiconductor device according to claim 12, wherein the oxide semiconductor contains a crystal of In₂Ga₂ZnO₇.

19. The semiconductor device according to claim 12, wherein hydrogen concentration of the oxide semiconductor is less than or equal to 5×

10¹⁹ atoms/cm³.

20. The semiconductor device according to claim 12, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>—

13</sup> A.