Semiconductor memory cell having an oxide semiconductor transistor and erasable by ultraviolet light

• US 8,659,941 B2
• Filed: 11/22/2010
• Issued: 02/25/2014
• Est. Priority Date: 11/24/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kamata, Koichiro, Sekine, Yusuke
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US12/951,899
• Publication Number:
  US 20110122673A1
• Time in Patent Office: 1,191 Days
• Field of Search: 365/182, 365/174, 365/104, 365/103
• US Class Current: 365/182
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.

Claims

1. A semiconductor device comprising a memory cell, the memory cell including a first transistor and a second transistor,

wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode,

wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode,

wherein the second semiconductor layer includes an oxide semiconductor material,

wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, and

wherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with an ultraviolet light.

2. The semiconductor device according to claim 1, wherein a threshold voltage of the second transistor is configured to be changed by irradiating the second semiconductor layer with the ultraviolet light.

3. The semiconductor device according to claim 1, wherein the second transistor is made a normally-on transistor by irradiating the second semiconductor layer with the ultraviolet light.

4. The semiconductor device according to claim 1, wherein the second semiconductor layer is located above the first semiconductor layer.

5. The semiconductor device according to claim 1, wherein the second source electrode is in contact with a bottom surface of the second semiconductor layer.

6. A semiconductor device comprising a first memory cell and a second memory cell,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode,

wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode,

wherein the second semiconductor layer includes a first oxide semiconductor material,

wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode and a first electrode of the first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein the third transistor comprises a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode,

wherein the fourth transistor comprises a fourth semiconductor layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode,

wherein the fourth semiconductor layer includes a second oxide semiconductor material,

wherein one of the fourth source electrode and the fourth drain electrode is electrically connected to the third gate electrode and a first electrode of the second capacitor,

wherein one of the first source electrode and the first drain electrode is electrically connected to one of the third source electrode and the third drain electrode,

wherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with a first ultraviolet light, and

wherein charge accumulated in the third gate electrode is discharged by irradiating the fourth semiconductor layer with a second ultraviolet light.

7. The semiconductor device according to claim 6, wherein a threshold voltage of the second transistor is configured to be changed by irradiating the second semiconductor layer with the first ultraviolet light.

8. The semiconductor device according to claim 6, wherein the second transistor is made a normally-on transistor by irradiating the second semiconductor layer with the first ultraviolet light.

9. The semiconductor device according to claim 6, wherein the second semiconductor layer is located over the first semiconductor layer.

10. The semiconductor device according to claim 6, wherein the second source electrode is in contact with a bottom surface of the second semiconductor layer.

11. The semiconductor device according to claim 6, wherein a conductive layer includes the one of the first source electrode and the first drain electrode and the one of the third source electrode and the third drain electrode.

12. The semiconductor device according to claim 6, wherein the first ultraviolet light and the second ultraviolet light are emitted at the same time.

13. The semiconductor device according to claim 6, wherein the first oxide semiconductor material is the second oxide semiconductor material.