Storage unit for communication system node, method for data storage and communication system node

• US 8,660,131 B2
• Filed: 06/06/2006
• Issued: 02/25/2014
• Est. Priority Date: 06/09/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Vermunt, Franciscus Maria, Vos, Antonius Maria, Heuts, Patrick Willem
• Primary Examiner(s): Ton, Dang T
• Assistant Examiner(s): Preval, Lionel
• Application Number:
  US11/916,682
• Publication Number:
  US 20100220735A1
• Time in Patent Office: 2,821 Days
• Field of Search: 370/401, 370/458, 370/244, 710/36, 710/263, 701/1, 701/76, 711/154, 709/224
• US Class Current: 370/401
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

The present invention relates to a data storage unit for a communication system node, a method for data storage and a communication system node. More particularly it relates to storing buffering data and control data in a unit located outside of a Communication Controller on system or host-controller level, wherein a time-triggered protocol runs on the node. By locating control and buffering related data, including format and behavior, outside the Communication Controller it becomes far more flexible, extendable, and re-configurable as data buffering related restrictions, e.g. buffer sizes and number of buffers, are moved from Communication Controller level to system level.

Claims

1. A system comprising:

a host controller;

a general memory unit on a host-controller level;

a communication controller, wherein a time-triggered protocol launches network activity in predefined time slots; and

a storage unit for configuration and buffering related data that is provided outside of the communication controller on a system level, wherein the storage unit further comprises;

a slot control list, a buffer control list, a buffer descriptor list, a first address calculation unit provided between the slot control list and the buffer control list, and a second address calculation unit provided between the buffer control list and the buffer descriptor list.

2. The system according to claim 1, wherein the storage unit further comprises:

a frame buffer that holds at least frame data.

3. The system according to claim 2, wherein the slot control list provides a definition of both relevance and purpose of communication controller time slots to the system, and holds a logical link.

4. The system according to claim 2, wherein the buffer control list provides a definition of a behavior, holds the status of a buffer, and holds a logical link to the buffer-entries of the buffer.

5. The system according to claim 2, wherein the buffer descriptor list provides a definition of characteristics of a buffer entry and holds a logical link to the frame buffer.

6. The system according to claim 2, wherein the frame buffer provides a storage area that holds at least frame data.

7. The system according to claim 1, wherein the storage unit is general-purpose logic.

8. The system according to claim 1, wherein the storage unit is located inside said general memory unit.

9. The system according to claim 1, wherein the communication controller incorporates a dedicated logic for data retrieval, interpretation, execution, and status update.

10. The system according to claim 2, wherein the communication controller is provided with a slot control list addressing unit linked to the slot control list to address entries in the slot control list.

11. The system according to claim 1, wherein the communication controller is provided with a buffer control list addressing unit to address entries in the buffer control list, wherein the buffer control list addressing unit is linked to said first address calculation unit between the slot control list and the buffer control list.

12. The system according to claim 1, wherein the communication controller is provided with a buffer descriptor list addressing unit to address entries in said buffer descriptor list, wherein the buffer descriptor list addressing unit is linked to said second address calculation unit between the buffer control list and the buffer descriptor list.

13. The system according to claim 1, wherein the communication controller is a FlexRay Data Link Controller.

14. The system according to claim 1, wherein the time-triggered protocol is a FlexRay protocol.

15. A data storage device within a communication system, for configuration and buffering related data that is provided outside of a communication controller on a system level, wherein the communication system is provided with active time slots and at least one logical buffer, the data storage device comprising:

a slot control list to associate communication controller time slots to their respective buffers;

a buffer control list, wherein a buffer control list offset is in a slot control list entry;

a buffer descriptor list, wherein a buffer descriptor list offset is in a buffer control list entry; and

a frame buffer that holds at least frame data.

16. A method for data storage for control and buffering related data within a communication system for time-triggered communication protocols, comprising:

addressing an entry of a slot control list through a communication controller;

linking the slot control list entry to a buffer control list entry to associate a time slot to a buffer, wherein a buffer control list offset is in the slot control list entry;

addressing the buffer control list entry through said communication controller;

linking the buffer control list entry to a buffer descriptor list entry to associate the buffer to the buffer descriptor list entry, wherein a buffer descriptor list offset is in the buffer control list entry;

addressing the buffer descriptor list entry through said communication controller;

linking said buffer descriptor list entry to a frame buffer; and

addressing the frame buffer through said communication controller.

17. The method of claim 16, wherein accessing said slot control list further comprises:

adding an offset associated with a slot control list base address.

18. The method of claim 16, wherein linking said slot control list to the buffer control list further comprises:

adding an offset associated with a buffer control list base address in a first address calculation unit.

19. The method of claim 16, wherein linking said buffer control list with said buffer descriptor list further comprises:

adding an offset associated with a buffer descriptor list base address in a second address calculation unit.