Image processing apparatus implemented in IC chip

• US 8,660,190 B2
• Filed: 05/19/2006
• Issued: 02/25/2014
• Est. Priority Date: 06/01/2001
• Status: Expired due to Fees

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Inventors: Okada, Shigeyuki
• Primary Examiner(s): DIEP, NHON THANH
• Application Number:
  US11/436,519
• Publication Number:
  US 20060203918A1
• Time in Patent Office: 2,839 Days
• Field of Search: None
• US Class Current: 375/240.25
• CPC Class Codes: H04N 5/783 Adaptations for reproducing at a rate different from the recording rate
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

When a reverse reproduction is instructed, an MPEG video stream is once decoded and is converted to image video signals by a first display circuit. Thereafter, the image video signals are again recoded by an image input circuit and an MPEG video encoder, so as to be overwritten in a storage area of a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively. Then the thus decoded data are converted to image video signals by a second display circuit, so as to be displayed on a display.

Claims

1. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence read from a hard disk;

a first frame memory for temporarily storing decoded data; and

a first display circuit which generates an image video signal for forward reproduction from data inputted from the first frame memory in succession;

a second block including;

an image input circuit which converts the image video signal, outputted from said first block, to a video data sequence;

a second frame memory for storing the video data sequence temporarily; and

an encoder which codes the video data sequence inputted from the second frame memory in succession into a second coded data sequence and outputs the second coded data to a predetermined storage area in the hard disk; and

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from the storage area in a reverse time-series manner;

a third frame memory for storing decoded data temporarily; and

a second display circuit which generates an image video signal for reverse reproduction from data inputted from the third frame memory in succession, wherein

the second block generates the second coded data sequence and outputs the second coded data sequence to the storage area in the storage device during forward reproduction.

2. An image processing apparatus according to claim 1, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

3. An image processing apparatus according to claim 1, the first coded data sequence is coded in compliance with MPEG.

4. The image processing apparatus according to claim 1, wherein the storage area is an area for storing coded data for 1 group of pictures (GOP) or 2 groups of pictures (GOP).