Parallel, pipelined, integrated-circuit implementation of a computational engine
First Claim
1. A integrated-circuit video codec comprising:
- processing-element subcomponents, each of which carries out a high-level computational step of a stepwise computational process, the processing-element subcomponents arranged in one or more assembly-line-like series, which operate concurrently on different computational objects;
an object cache that stores computational objects, the computational objects comprising data-structure values input to processing elements prior to each high-level computational step and output from processing elements during each high-level computational step; and
an object bus that provides computational-object-level transmission transactions and through which computational objects are exchanged between the processing elements and the object cache.
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Abstract
Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.
14 Citations
18 Claims
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1. A integrated-circuit video codec comprising:
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processing-element subcomponents, each of which carries out a high-level computational step of a stepwise computational process, the processing-element subcomponents arranged in one or more assembly-line-like series, which operate concurrently on different computational objects; an object cache that stores computational objects, the computational objects comprising data-structure values input to processing elements prior to each high-level computational step and output from processing elements during each high-level computational step; and an object bus that provides computational-object-level transmission transactions and through which computational objects are exchanged between the processing elements and the object cache. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification