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Reduced frequency data processing using a matched filter set front end

  • US 8,660,220 B2
  • Filed: 09/05/2008
  • Issued: 02/25/2014
  • Est. Priority Date: 09/05/2008
  • Status: Active Grant
First Claim
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1. A reduced clock rate data decoding circuit, the circuit comprising:

  • a matched filter bank, wherein the matched filter bank receives a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence; and

    a detector circuit, wherein the detector circuit processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock, wherein the reduced rate clock is the sample clock divided by a factor.

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