Reduced frequency data processing using a matched filter set front end

• US 8,660,220 B2
• Filed: 09/05/2008
• Issued: 02/25/2014
• Est. Priority Date: 09/05/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Noeldner, David
• Primary Examiner(s): Ahn, Sam K
• Assistant Examiner(s): Ali, Shawkat M
• Application Number:
  US12/205,819
• Publication Number:
  US 20100061492A1
• Time in Patent Office: 1,999 Days
• Field of Search: 375/148, 375/343, 375/341, 375/371, 370/338, 370/280, 340/825.72, 326/8, 342/463, 360/39, 360/46, 455/296
• US Class Current: 375/343
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 25/03248 Arrangements for operating in conjunction with other apparatus
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.

Claims

1. A reduced clock rate data decoding circuit, the circuit comprising:

a matched filter bank, wherein the matched filter bank receives a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence; and

a detector circuit, wherein the detector circuit processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock, wherein the reduced rate clock is the sample clock divided by a factor.

2. The circuit of claim 1, wherein the first matched filter and the second matched filter are finite impulse response filters.

3. The circuit of claim 1, wherein the matched filter bank further includes a third matched filter tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and a fourth matched filter tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence;

and wherein the series of symbol proxies further includes the third symbol proxy and the fourth symbol proxy.

4. The circuit of claim 3, wherein the first bit sequence is ‘

00’

, the second bit sequence is ‘

01’

, the third bit sequence is ‘

10’ and

the fourth bit sequence is ‘

11’

; and

wherein the factor is two.

5. The circuit of claim 1, wherein the matched filter bank further includes a third matched filter tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, a fourth matched filter tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence, a fifth matched filter tuned to detect a fifth bit sequence in the series of symbols and to assert a fifth symbol proxy upon detection of the fifth bit sequence, a sixth matched filter tuned to detect a sixth bit sequence in the series of symbols and to assert a sixth symbol proxy upon detection of the sixth bit sequence, a seventh matched filter tuned to detect a seventh bit sequence in the series of symbols and to assert a seventh symbol proxy upon detection of the seventh bit sequence, and an eighth matched filter tuned to detect an eighth bit sequence in the series of symbols and to assert an eighth symbol proxy upon detection of the eighth bit sequence;

and wherein the series of symbol proxies further includes the third symbol proxy, the fourth symbol proxy, the fifth symbol proxy, the sixth symbol proxy, the seventh symbol proxy and the eighth symbol proxy.

6. The circuit of claim 5, wherein the first bit sequence is ‘

000’

, the second bit sequence is ‘

001’

, the third bit sequence is ‘

010’

, the fourth bit sequence is ‘

011’

, the fifth bit sequence is ‘

100’

, the sixth bit sequence is ‘

101’

, the seventh bit sequence is ‘

110’ and

the eighth bit sequence is ‘

111’

; and

wherein the factor is three.

7. The circuit of claim 1, wherein the circuit further comprises:

an analog to digital converter, wherein the analog to digital converter is operable to receive an analog input and to provide a series of digital samples of the analog input; and

a filter, wherein the filter is operable to receive the series of digital samples, to filter noise associated with the series of digital samples, and to provide the series of symbols.

8. The circuit of claim 7, wherein the noise includes inter symbol interference.

9. The circuit of claim 1, wherein the detector is a Viterbi algorithm detector.

10. The circuit of claim 1, wherein each of the first symbol proxy and the second symbol proxy include a predicted level and confidence information indicating a degree of confidence in the predicted level.

11. A method for data detection using a reduced rate clock, the method comprising:

receiving a series of symbols at a rate corresponding to an input clock;

filtering the series of symbols in parallel through a first matched filter, a second matched filter, a third matched filter and a fourth matched filter; and

wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence, the third matched filter is tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and the fourth matched filter is tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence; and

performing a data detection on a series of symbol proxies including the first symbol proxy, the second symbol proxy, the third symbol proxy and the fourth symbol proxy at a rate corresponding to the input clock divided by a factor.

12. The method of claim 11, wherein the first bit sequence is ‘

00’

, the second bit sequence is ‘

01’

, the third bit sequence is ‘

10’ and

the fourth bit sequence is ‘

11’

; and

wherein the factor is two.

13. The method of claim 11, wherein filtering the series of symbols in parallel further includes filtering the series of symbols through a fifth matched filter tuned to detect a fifth bit sequence in the series of symbols and to assert a fifth symbol proxy upon detection of the fifth bit sequence, a sixth matched filter tuned to detect a sixth bit sequence in the series of symbols and to assert a sixth symbol proxy upon detection of the sixth bit sequence, a seventh matched filter tuned to detect a seventh bit sequence in the series of symbols and to assert a seventh symbol proxy upon detection of the seventh bit sequence, and an eighth matched filter tuned to detect an eighth bit sequence in the series of symbols and to assert an eighth symbol proxy upon detection of the eighth bit sequence;

and wherein the series of symbol proxies further includes the fifth symbol proxy, the sixth symbol proxy, the seventh symbol proxy, and the eighth symbol proxy.

14. The method of claim 13, wherein the first bit sequence is ‘

000’

, the second bit sequence is ‘

001’

, the third bit sequence is ‘

010’

, the fourth bit sequence is ‘

011’

, the fifth bit sequence is ‘

100’

, the sixth bit sequence is ‘

101’

, the seventh bit sequence is ‘

110’ and

the eighth bit sequence is ‘

111’

; and

wherein the factor is three.

15. The method of claim 11, wherein the method further comprises:

receiving an analog signal;

performing an analog to digital conversion on the analog signal to generate a series of digital samples representing the analog signal; and

filtering the series of digital samples to yield the series of symbols.

16. The method of claim 15, wherein the analog to digital conversion is done at a rate corresponding to the input clock.

17. A communication system including a receiver with a reduced rate data detector, the system comprising:

a receiver, wherein the receiver includes;

an analog to digital converter, wherein the analog to digital converter is operable to receive an analog signal and to generate a series of digital samples representing the analog signal at a rate corresponding to an input clock;

a matched filter bank, wherein the matched filter bank is operable to receive a series of symbols derived from the series of digital samples and to filter the received series of symbols through a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence, a third matched filter tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and a fourth matched filter tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence; and

a detector, wherein the detector is operable to process a series of symbol proxies including the first symbol proxy, the second symbol proxy, the third symbol proxy and the fourth symbol proxy at a rate corresponding to the input clock divided by a factor.

18. The system of claim 17, wherein the factor is an integer value larger than one.

19. The communication system of claim 17, wherein the analog signal is transmitted by a transmitter to the receiver via a transfer medium, wherein the communication system is a hard disk drive system, and wherein the transfer medium is a magnetic storage medium.

20. The communication system of claim 17, wherein the analog signal is transmitted by a transmitter to the receiver via a transfer medium, wherein the communication system is a wireless communication system, and wherein the transfer medium is an atmosphere through which a radio frequency signal is transmitted.