Multifunction receiver-on-chip for electronic warfare applications

• US 8,660,671 B2
• Filed: 04/20/2012
• Issued: 02/25/2014
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Stroili, Frank D., Huggett, James M.
• Primary Examiner(s): Bahta, Kidest
• Application Number:
  US13/451,620
• Publication Number:
  US 20120201545A1
• Time in Patent Office: 676 Days
• Field of Search: 700/29, 700/90, 700/302, 701/11, 257/728, 370/269, 370/265, 370/266, 455/524, 455/525, 244/117.11, 244/118.1, 244/129, 343/705
• US Class Current: 700/90
• CPC Class Codes: G01S 7/032 Constructional details for solid-state radar subsystems
• CPC Class Codes: G01S 7/38 Jamming means, e.g. producing false echoes

Abstract

What is provided is a receiver-on-a-chip comprising a monolithic integrated circuit that reduces the receiver to a cigarette-pack-sized assembly mountable directly at an antenna element, with a much-increased operational bandwidth and instantaneous bandwidth, increased dynamic range and with a two-order-of-magnitude decrease in size and weight. Moreover, because of the elimination of all of the I/O drivers and attendant circuitry, power consumption is reduced by two-thirds, whereas the mean time before failure is increased to 10,000 hours due to the robustness of the monolithic integrated circuit and use of fiber optics.

Claims

1. An electronic warfare receiver system light and small enough to be located on an unmanned aerial vehicle and having a power consumption minimized to maximize endurance, comprising:

an array of antenna elements on said unmanned aerial vehicle;

a lightweight monolithic broadband receiver-on-a-chip located at each antenna element;

fiber optic cables coupled at one end to the output of respective receivers-on-a-chip; and

,

a processor coupled to the other ends of said fiber optic cables for processing the individual outputs of said receiver-on-a-chip, wherein each of said receivers-on-a-chip has a volume of less than 7 cubic inches, and each of said receivers-on-a-chip weighs less than a pound.

2. The system of claim 1, wherein there are no I/O drivers between the circuits on said receiver-on-a-chip, whereby the power consumption of said receiver-on-a-chip can be made less than 10 watts.

3. The system of claim 1, wherein said broadband receiver-on-a-chip manufactured in a monolithic process using silicon-germanium transistor technology so as to produce transistor switching speeds in excess of 100 GHz to effectuate a 0.03 GHz to 18 GHz operational bandwidth.

4. The system of claim 3, wherein said receiver-on-a-chip includes super high-speed analog-to-digital converters running at over 100 GHz to reduce the requirement for numbers of IF stages including down-converters and local oscillators.